Terabit Ethernet
Terabit Ethernet or TbE is Ethernet with speeds above 100 Gigabit Ethernet. 400 Gigabit Ethernet (400G, 400GbE) and 200 Gigabit Ethernet (200G, 200GbE)[1] standards developed by the IEEE P802.3bs Task Force using broadly similar technology to 100 Gigabit Ethernet[2][3] were approved on December 6, 2017.[4][5] In 2016, several networking equipment suppliers were already offering proprietary solutions for 200G and 400G.[5]
The Ethernet Alliance's 2022 technology roadmap expects speeds of 800 Gbit/s and 1.6 Tbit/s to become an IEEE standard between about 2023 and 2025.[6][7] Doubling to 800 GbE is expected to occur after 112 Gbit/s SerDes become available. The Optical Internetworking Forum (OIF) has already announced five new projects at 112 Gbit/s which would also make 4th generation (single-lane) 100 GbE links possible.[8] The IEEE P802.3df Task Force started work in January 2022 to standardize 800 Gbit/s and 1.6 Tbit/s Ethernet. [9]
History
Facebook and Google, among other companies, have expressed a need for TbE.[10] While a speed of 400 Gbit/s is achievable with existing technology, 1 Tbit/s (1000 Gbit/s) would require different technology.[2][11] Accordingly, at the IEEE Industry Connections Higher Speed Ethernet Consensus group meeting in September 2012, 400 GbE was chosen as the next generation goal.[2] Additional 200 GbE objectives were added in January 2016.
The University of California, Santa Barbara (UCSB) attracted help from Agilent Technologies, Google, Intel, Rockwell Collins, and Verizon Communications to help with research into next generation Ethernet.[12]
As of early 2016, chassis/modular based core router platforms from Cisco, Juniper and other major manufacturers support 400 Gbit/s full duplex data rates per slot. One, two and four port 100 GbE and one port 400 GbE line cards are presently available. As of early 2019, 200 GbE line cards became available after 802.3cd standard ratification.[13][14]
200G Ethernet uses PAM4 signaling which allows 2 bits to be transmitted per clock cycle, but at a higher implementation cost.[15]
Standards development
The IEEE formed the "IEEE 802.3 Industry Connections Ethernet Bandwidth Assessment Ad Hoc", to investigate the business needs for short and long term bandwidth requirements.[16][17][18]
IEEE 802.3's "400 Gb/s Ethernet Study Group" started working on the 400 Gbit/s generation standard in March 2013.[19] Results from the study group were published and approved on March 27, 2014. Subsequently, the IEEE 802.3bs Task Force[20] started working to provide physical layer specifications for several link distances.[21]
The IEEE 802.3bs standard was approved on December 6, 2017[4] and is available online.[22]
The IEEE 802.3cd standard was approved on December 5, 2018.
The IEEE 802.3cn standard was approved on December 20, 2019.
The IEEE 802.3cm standard was approved on January 30, 2020.
The IEEE 802.3cu standard was approved on February 11, 2021.
The IEEE 802.3ck and 802.3db standards were approved on September 21, 2022.
In November 2022 the IEEE 802.3df project objectives were split in two, with 1.6T and 200G/lane work being moved to the new IEEE 802.3dj project
- Original IEEE P802.3df Objectives
- Updated IEEE P802.3df Objectives to reduce scope to 800G Ethernet using 100G physical lanes
- IEEE P802.3dj Objectives for 1.6Tbit/s Ethernet and PHYs that employ 200Gbit/s lanes
IEEE project objectives
Like all speeds since 10 Gigabit Ethernet, the standards support only full-duplex operation. Other objectives include:[21]
- Support MAC data rates of 400 Gbit/s and 200 Gbit/s[1]
- Preserve the Ethernet frame format utilizing the Ethernet MAC
- Preserve minimum and maximum frame size of current Ethernet standard
- Support a bit error ratio (BER) of 10−13, which is an improvement over the 10−12 BER that was specified for 10GbE, 40GbE, and 100GbE.
- Support for OTN (transport of Ethernet across optical transport networks), and optional support for Energy-Efficient Ethernet (EEE).
802.3bs project
Define physical layer specifications supporting:[21]
- 400 Gbit/s Ethernet
- at least 100 m over multi-mode fiber (400GBASE-SR16) using 16 parallel strands of fiber each at 25 Gbit/s[23][24]
- at least 500 m over single-mode fiber (400GBASE-DR4) using 4 parallel strands of fiber each at 100 Gbit/s[25][26]
- at least 2 km over single-mode fiber (400GBASE-FR8) using 8 parallel wavelengths (CWDM) each at 50 Gbit/s[25][27][28]
- at least 10 km over single-mode fiber (400GBASE-LR8) using 8 parallel wavelengths (CWDM) each at 50 Gbit/s[25][28][29]
- 8 and 16 lane chip-to-chip/chip-to-module electrical interfaces (400GAUI-8 and 400GAUI-16)
- 200 Gbit/s Ethernet
- at least 500 m over single-mode fiber (200GBASE-DR4) using 4 parallel strands of fiber each at 50 Gbit/s[30][31]
- at least 2 km over single-mode fiber (200GBASE-FR4) using 4 parallel wavelengths (CWDM) each at 50 Gbit/s[1][31]
- at least 10 km over single-mode fiber (200GBASE-LR4) using 4 parallel wavelengths (CWDM) each at 50 Gbit/s[1][31]
- 4 or 8 lane chip-to-chip/chip-to-module electrical interfaces (200GAUI-4 and 200GAUI-8)
802.3cd project
- Define four-lane 200 Gbit/s PHYs for operation over:
- copper twin-axial cables with lengths up to at least 3 m (200GBASE-CR4).
- printed circuit board backplane with a total channel insertion loss of ≤ 30 dB at 13.28125 GHz (200GBASE-KR4).
- Define 200 Gbit/s PHYs for operation over MMF with lengths up to at least 100 m (200GBASE-SR4).
802.3ck project
- 200 Gbit/s Ethernet
- Define a two-lane 200 Gbit/s Attachment Unit interface (AUI) for chip-to-module applications, compatible with PMDs based on 100 Gbit/s per lane optical signaling (200GAUI-2 C2M)
- Define a two-lane 200 Gbit/s Attachment Unit Interface (AUI) for chip-to-chip applications (200GAUI-2 C2C)
- Define a two-lane 200 Gbit/s PHY for operation over electrical backplanes an insertion loss ≤ 28 dB at 26.56 GHz (200GBASE-KR2)
- Define a two-lane 200 Gbit/s PHY for operation over twin axial copper cables with lengths up to at least 2 m (200GBASE-CR2)
- 400 Gbit/s Ethernet
- Define a four-lane 400 Gbit/s Attachment Unit interface (AUI) for chip-to-module applications, compatible with PMDs based on 100 Gbit/s per lane optical signaling (400GAUI-4 C2M)
- Define a four-lane 400 Gbit/s Attachment Unit Interface (AUI) for chip-to-chip applications (400GAUI-4 C2C)
- Define a four-lane 400 Gbit/s PHY for operation over electrical backplanes an insertion loss ≤ 28 dB at 26.56 GHz (400GBASE-KR4)
- Define a four-lane 400 Gbit/s PHY for operation over twin axial copper cables with lengths up to at least 2 m (400GBASE-CR4)
802.3cm project
- 400 Gbit/s Ethernet
- Define a physical layer specification supporting 400 Gbit/s operation over 8 pairs of MMF with lengths up to at least 100 m (400GBASE-SR8)
- Define a physical layer specification supporting 400 Gbit/s operation over 4 pairs of MMF with lengths up to at least 100 m (400GBASE-SR4.2)
802.3cn project
- 200 Gbit/s Ethernet
- Provide a physical layer specification supporting 200 Gbit/s operation over four wavelengths capable of at least 40 km of SMF (200GBASE-ER4) [32]
- 400 Gbit/s Ethernet
- Provide a physical layer specification supporting 400 Gbit/s operation over eight wavelengths capable of at least 40 km of SMF (400GBASE-ER8)[32]
802.3cu project
- Define a four-wavelength 400 Gbit/s PHY for operation over SMF with lengths up to at least 2 km (400GBASE-FR4)
- Define a four-wavelength 400 Gbit/s PHY for operation over SMF with lengths up to at least 6 km (400GBASE-LR4-6) [33]
802.3cw project
802.3db project
- 200 Gbit/s Ethernet
- Define a physical layer specification that supports 200 Gbit/s operation over 2 pairs of MMF with lengths up to at least 50 m (200GBASE-VR2)
- Define a physical layer specification that supports 200 Gbit/s operation over 2 pairs of MMF with lengths up to at least 100 m (200GBASE-SR2)
- 400 Gbit/s Ethernet
- Define a physical layer specification that supports 400 Gbit/s operation over 4 pairs of MMF with lengths up to at least 50 m (400GBASE-VR4)
- Define a physical layer specification that supports 400 Gbit/s operation over 4 pairs of MMF with lengths up to at least 100 m (400GBASE-SR4)
'IEEE P802.3db 100 Gb/s, 200 Gb/s, and 400 Gb/s Short Reach Fiber Task Force'
802.3df project
- Adds 800G Ethernet rate and specifies port types using existing 100G per lane technology
IEEE P802.3df Objectives for 800Gbit/s Ethernet and 400G and 800G PHYs using 100Gbit/s lanes
802.3dj project
- Adds 1.6T Ethernet rate and specifies port types using new 200G per lane technology
200G port types
| Fibre type | Introduced | Performance |
|---|---|---|
| MMF FDDI 62.5/125 µm | 1987 | 160 MHz·km @ 850 nm |
| MMF OM1 62.5/125 µm | 1989 | 200 MHz·km @ 850 nm |
| MMF OM2 50/125 µm | 1998 | 500 MHz·km @ 850 nm |
| MMF OM3 50/125 µm | 2003 | 1500 MHz·km @ 850 nm |
| MMF OM4 50/125 µm | 2008 | 3500 MHz·km @ 850 nm |
| MMF OM5 50/125 µm | 2016 | 3500 MHz·km @ 850 nm + 1850 MHz·km @ 950 nm |
| SMF OS1 9/125 µm | 1998 | 1.0 dB/km @ 1300/1550 nm |
| SMF OS2 9/125 µm | 2000 | 0.4 dB/km @ 1300/1550 nm |
| Name | Standard | Status | Media | Connector | Transceiver Module |
Reach in m |
# Media (⇆) |
# Lambdas (→) |
# Lanes (→) |
Notes |
|---|---|---|---|---|---|---|---|---|---|---|
| 200 Gigabit Ethernet (200 GbE) (1st Generation: 25GbE-based) - (Data rate: 200 Gbit/s - Line code: 256b/257b × RS-FEC(544,514) × NRZ - Line rate: 8x 26.5625 GBd = 212.5 GBd - Full-Duplex) [37][38][39] | ||||||||||
| 200GAUI-8 | 802.3bs-2017 (CL120B/C) |
current | Chip-to-chip/ Chip-to-module interface |
— | — | 0.25 | 16 | N/A | 8 | PCBs |
| 200 Gigabit Ethernet (200 GbE) (2nd Generation: 50GbE-based) - (Data rate: 200 Gbit/s - Line code: 256b/257b × RS-FEC(544,514) × PAM4 - Line rate: 4x 26.5625 GBd x2 = 212.5 GBd - Full-Duplex) [37][38][39] | ||||||||||
| 200GAUI-4 | 802.3bs-2017 (CL120D/E) |
current | Chip-to-chip/ Chip-to-module interface |
— | — | 0.25 | 8 | N/A | 4 | PCBs |
| 200GBASE-KR4 | 802.3cd-2018 (CL137) |
current | Cu-Backplane | — | — | 1 | 8 | N/A | 4 | PCBs; total insertion loss of ≤ 30 dB at 13.28125 GHz |
| 200GBASE-CR4 | 802.3cd-2018 (CL136) |
current | twinaxial copper cable |
QSFP-DD, QSFP56, microQSFP, OSFP |
N/A | 3 | 8 | N/A | 4 | Data centres (in-rack) |
| 200GBASE-SR4 | 802.3cd-2018 (CL138) |
current | Fibre 850 nm |
MPO/MTP (MPO-12) |
QSFP56 | OM3: 70 | 8 | 1 | 4 | uses four fibers in each direction |
| OM4: 100 | ||||||||||
| 200GBASE-DR4 | 802.3bs-2017 (CL121) |
current | Fibre 1304.5 – 1317.5 nm |
MPO/MTP (MPO-12) |
QSFP56 | OS2: 500 | 8 | 1 | 4 | uses four fibers in each direction |
| 200GBASE-FR4 | 802.3bs-2017 (CL122) |
current | Fibre 1271 – 1331 nm |
LC | QSFP56 | OS2: 2k | 2 | 4 | 4 | WDM |
| 200GBASE-LR4 | 802.3bs-2017 (CL122) |
current | Fibre 1295.56 – 1309.14 nm |
LC | QSFP56 | OS2: 10k | 2 | 4 | 4 | WDM |
| 200GBASE-ER4 | 802.3cn-2019 (CL122) |
current | Fibre 1295.56 – 1309.14 nm |
LC | QSFP56 | OS2: 40k | 2 | 4 | 4 | WDM |
| 200 Gigabit Ethernet (200 GbE) (3rd Generation: 100GbE-based) - (Data rate: 200 Gbit/s - Line code: 256b/257b × RS-FEC(544,514) × PAM4 - Line rate: 2x 53.1250 GBd x2 = 212.5 GBd - Full-Duplex) [37][38][39] | ||||||||||
| 200GAUI-2 | 802.3ck-2022 (CL120F/G) |
current | Chip-to-chip/ Chip-to-module interface |
— | N/A | 0.25 | 4 | N/A | 2 | PCBs |
| 200GBASE-KR2 | 802.3ck-2022 (CL163) |
current | Cu backplane | — | — | 1 | 4 | N/A | 2 | PCBs; total insertion loss of ≤ 28 dB at 26.56 GHz |
| 200GBASE-CR2 | 802.3ck-2022 (CL162) |
current | twinaxial copper cable | QSFP-DD, QSFP112, SFP-DD112, DSFP, OSFP |
N/A | 2 | 4 | N/A | 2 | |
| 200GBASE-VR2 | 802.3db-2022 (CL167) |
current | Fiber 850 nm |
MPO (MPO-12) |
QSFP QSFP-DD SFP-DD112 |
OM3: 30 | 4 | 1 | 2 | |
| OM4: 50 | ||||||||||
| 200GBASE-SR2 | 802.3db-2022 (CL167) |
current | Fiber 850 nm |
MPO (MPO-12) |
QSFP QSFP-DD SFP-DD112 |
OM3: 60 | 4 | 1 | 2 | |
| OM4: 100 | ||||||||||
400G port types
| Fibre type | Introduced | Performance |
|---|---|---|
| MMF FDDI 62.5/125 µm | 1987 | 160 MHz·km @ 850 nm |
| MMF OM1 62.5/125 µm | 1989 | 200 MHz·km @ 850 nm |
| MMF OM2 50/125 µm | 1998 | 500 MHz·km @ 850 nm |
| MMF OM3 50/125 µm | 2003 | 1500 MHz·km @ 850 nm |
| MMF OM4 50/125 µm | 2008 | 3500 MHz·km @ 850 nm |
| MMF OM5 50/125 µm | 2016 | 3500 MHz·km @ 850 nm + 1850 MHz·km @ 950 nm |
| SMF OS1 9/125 µm | 1998 | 1.0 dB/km @ 1300/1550 nm |
| SMF OS2 9/125 µm | 2000 | 0.4 dB/km @ 1300/1550 nm |
| Name | Standard | Status | Media | Connector | Transceiver Module |
Reach in m |
# Media (⇆) |
# λ (→) |
# Lanes (→) |
Notes |
|---|---|---|---|---|---|---|---|---|---|---|
| 400 Gigabit Ethernet (400 GbE) (1st Generation: 25GbE-based) - (Data rate: 400 Gbit/s - Line code: 256b/257b × RS-FEC(544,514) × NRZ - Line rate: 16x 26.5625 GBd = 425 GBd - Full-Duplex) [37] | ||||||||||
| 400GAUI-16 | 802.3bs-2017 (CL120B/C) |
current | Chip-to-chip/ Chip-to-module interface |
— | — | 0.25 | 32 | N/A | 16 | PCBs |
| 400GBASE-SR16 | 802.3bs-2017 (CL123) |
current | Fibre 850 nm |
MPO/MTP (MPO-32) |
CFP8 | OM3: 70 | 32 | 1 | 16 | |
| OM4: 100 | ||||||||||
| OM5: 100 | ||||||||||
| 400 Gigabit Ethernet (400 GbE) (2nd Generation: 50GbE-based) - (Data rate: 400 Gbit/s - Line code: 256b/257b × RS-FEC(544,514) × PAM4 - Line rate: 8x 26.5625 GBd x2 = 425.0 GBd - Full-Duplex) [37] | ||||||||||
| 400GAUI-8 | 802.3bs-2017 (CL 120D/E) |
current | Chip-to-chip/ Chip-to-module interface |
— | — | 0.25 | 16 | N/A | 8 | PCBs |
| 400GBASE-KR8 | proprietary (ETC) (CL120) |
current | Cu-Backplane | — | — | 1 | 8 | N/A | 8 | WDM |
| 400GBASE-SR8 | 802.3cm-2020 (CL138) |
current | Fiber 850 nm |
MPO/MTP (MPO-16) |
QSFP-DD OSFP |
OM3: 70 | 16 | 1 | 8 | |
| OM4: 100 | ||||||||||
| OM5: 100 | ||||||||||
| 400GBASE-SR4.2 (Bidirectional) |
802.3cm-2020 (CL150) |
current | Fiber 850 nm 912 nm |
MPO/MTP (MPO-12) |
QSFP-DD | OM3: 70 | 8 | 2 | 8 | Bidirectional WDM |
| OM4: 100 | ||||||||||
| OM5: 150 | ||||||||||
| 400GBASE-FR8 | 802.3bs-2017 (CL122) |
current | Fibre 1273.54 – 1309.14 nm |
LC | QSFP-DD OSFP |
OS2: 2k | 2 | 8 | 8 | WDM |
| 400GBASE-LR8 | 802.3bs-2017 (CL122) |
current | Fibre 1273.54 – 1309.14 nm |
LC | QSFP-DD OSFP |
OS2: 10k | 2 | 8 | 8 | WDM |
| 400GBASE-ER8 | 802.3cn-2019 (CL122) |
current | Fibre 1273.54 – 1309.14 nm |
LC | QSFP-DD | OS2: 40k | 2 | 8 | 8 | WDM |
| 400 Gigabit Ethernet (400 GbE) (3rd Generation: 100GbE-based) - (Data rate: 400 Gbit/s - Line code: 256b/257b × RS-FEC(544,514) × PAM4 - Line rate: 4x 53.1250 GBd x2 = 425.0 GBd - Full-Duplex) [37] | ||||||||||
| 400GAUI-4 | 802.3ck-2022 (CL120F/G) |
current | Chip-to-chip/ Chip-to-module interface |
— | — | 0.25 | 8 | N/A | 4 | PCBs |
| 400GBASE-KR4 | 802.3ck-2022 (CL163) |
current | Cu-Backplane | — | — | 1 | 8 | N/A | 4 | PCBs; total insertion loss of ≤ 28 dB at 26.56 GHz |
| 400GBASE-CR4 | 802.3ck-2022 (CL162) |
current | twinaxial copper cable |
QSFP-DD, QSFP112, OSFP |
N/A | 2 | 8 | N/A | 4 | Data centres (in-rack) |
| 400GBASE-VR4 | 802.3db-2022 (CL167) |
current | Fibre 850 nm |
MPO (MPO-12) |
QSFP-DD | OM3: 30 | 8 | 1 | 4 | |
| OM4: 50 | ||||||||||
| OM5: 50 | ||||||||||
| 400GBASE-SR4 | 802.3db-2022 (CL167) |
current | Fibre 850 nm |
MPO (MPO-12) |
QSFP-DD | OM3: 60 | 8 | 1 | 4 | |
| OM4: 100 | ||||||||||
| OM5: 100 | ||||||||||
| 400GBASE-DR4 | 802.3bs-2017 (CL124) |
current | Fibre 1304.5 – 1317.5 nm |
MPO/MTP (MPO-12) |
QSFP-DD OSFP |
OS2: 500 | 8 | 1 | 4 | |
| 400GBASE-DR4-2 | 802.3df (CL124) |
development | Fibre 1304.5 – 1317.5 nm |
MPO/MTP (MPO-12) |
QSFP-DD OSFP |
OS2: 2k | 8 | 1 | 4 | |
| 400GBASE-XDR4 400GBASE-DR4+ |
proprietary (non IEEE) |
current | Fibre 1304.5 – 1317.5 nm |
MPO/MTP (MPO-12) |
QSFP-DD OSFP |
OSx: 2k | 8 | 1 | 4 | |
| 400GBASE-FR4 | 802.3cu-2021 (CL151) |
current | Fibre 1271−1331 nm |
LC | QSFP-DD OSFP |
OS2: 2k | 2 | 4 | 4 | Multi-Vendor Standard[40] |
| 400GBASE-LR4-6 | 802.3cu-2021 (CL151) |
current | Fibre 1271−1331 nm |
LC | QSFP-DD | OS2: 6k | 2 | 4 | 4 | |
| 400GBASE-LR4-10 | proprietary (MSA, Sept 2020) |
current | Fibre 1271−1331 nm |
LC | QSFP-DD | OSx: 10k | 2 | 4 | 4 | Multi-Vendor Standard[41] |
| 400GBASE-ZR | 802.3cw (CL155/156) |
development | Fibre | LC | QSFP-DD OSFP |
OSx: 80k | 2 | 1 | 2 | 59.84375 Gigabaud (DP-16QAM) |
800G port types
| Fibre type | Introduced | Performance |
|---|---|---|
| MMF FDDI 62.5/125 µm | 1987 | 160 MHz·km @ 850 nm |
| MMF OM1 62.5/125 µm | 1989 | 200 MHz·km @ 850 nm |
| MMF OM2 50/125 µm | 1998 | 500 MHz·km @ 850 nm |
| MMF OM3 50/125 µm | 2003 | 1500 MHz·km @ 850 nm |
| MMF OM4 50/125 µm | 2008 | 3500 MHz·km @ 850 nm |
| MMF OM5 50/125 µm | 2016 | 3500 MHz·km @ 850 nm + 1850 MHz·km @ 950 nm |
| SMF OS1 9/125 µm | 1998 | 1.0 dB/km @ 1300/1550 nm |
| SMF OS2 9/125 µm | 2000 | 0.4 dB/km @ 1300/1550 nm |
| Name | Standard | Status | Media | Connector | Transceiver Module |
Reach in m |
# Media (⇆) |
# λ (→) |
# Lanes (→) |
Notes |
|---|---|---|---|---|---|---|---|---|---|---|
| 800 Gigabit Ethernet (800 GbE) (100GbE-based) - (Data rate: 800 Gbit/s - Line code: 256b/257b × RS-FEC(544,514) × PAM4 - Line rate: 8x 53.1250 GBd x2 = 425.0 GBd - Full-Duplex) [37] | ||||||||||
| 800GAUI-8 | 802.3df (CL120F/G) |
development | Chip-to-chip/ Chip-to-module interface |
— | — | 0.25 | 16 | N/A | 8 | PCBs |
| 800GBASE-KR8 | 802.3df (CL163) |
development | Cu-Backplane | — | — | 1 | 16 | N/A | 8 | PCBs; total insertion loss of ≤ 28 dB at 26.56 GHz |
| 800GBASE-CR8 | 802.3df (CL162) |
development | twinaxial copper cable |
QSFP−DD800 OSFP |
N/A | 2 | 16 | N/A | 8 | Data centres (in-rack) |
| 800GBASE-VR8 | 802.3df (CL167) |
development | Fibre 850 nm |
MPO (MPO-16) |
QSFP-DD OSFP |
OM3: 30 | 16 | 1 | 8 | |
| OM4: 50 | ||||||||||
| OM5: 50 | ||||||||||
| 800GBASE-SR8 | 802.3df (CL167) |
development | Fibre 850 nm |
MPO (MPO-16) |
QSFP-DD OSFP |
OM3: 60 | 16 | 1 | 8 | |
| OM4: 100 | ||||||||||
| OM5: 100 | ||||||||||
| 800GBASE-DR8 | 802.3df (CL124) |
development | Fibre 1304.5 – 1317.5 nm |
MPO/MTP (MPO-16) |
QSFP-DD OSFP |
OS2: 500 | 16 | 1 | 8 | |
| 800GBASE-DR8-2 | 802.3df (CL124) |
development | Fibre 1304.5 – 1317.5 nm |
MPO/MTP (MPO-16) |
QSFP-DD OSFP |
OS2: 2k | 16 | 1 | 8 | |
See also
References
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{{cite book}}:|journal=ignored (help) - 100 m MMF draft proposal
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- Charles E. Spurgeon (2014). Ethernet: The Definitive Guide (2nd ed.). O'Reilly Media. ISBN 978-1-4493-6184-6.
- "Exploring The IEEE 802 Ethernet Ecosystem" (PDF). IEEE. 2017-06-04. Retrieved 2018-08-29.
- "Multi-Port Implementations of 50/100/200GbE" (PDF). Brocade. 2016-05-22. Retrieved 2018-08-29.
- "100Gb/s Electrical Signaling" (PDF). IEEE 802.3 NEA Ad hoc. Retrieved 2021-12-08.
- Nowell, Mark. "400G-FR4 Technical Specification". 100glambda.com. 100G Lambda MSA Group. Retrieved 26 May 2021.
- Nowell, Mark. "400G-LR4-10 Technical Specification". 100glambda.com. 100G Lambda MSA Group. Retrieved 26 May 2021.
Further reading
- Chris Jablonski. "Researchers to develop 1 Terabit Ethernet by 2015". ZD Net. Retrieved October 9, 2011.
- Iljitsch van Beijnum (August 2011). "Speed matters: how Ethernet went from 3 Mbps to 100 Gbps... and beyond". Ars Technica. Retrieved October 9, 2011.
- Rick Merritt (May 9, 2011). "IEEE Looks beyond 100G Ethernet". The Cutting Edge. Retrieved October 9, 2011.
- Stephen Lawson (February 2, 2010). "Facebook Sees Need for Terabit Ethernet". PC World. Retrieved December 15, 2011.
- IEEE Reports
- "100 gigabit Ethernet and beyond". IEEE Optical Communications: Design, Technologies, and Applications. March 2010. doi:10.1109/MCOM.2010.5434372. ISSN 0163-6804.
- Elby, Stuart (July 2011). "The drive towards Terabit Ethernet". 2011 IEEE Photonics Society Summer Topical Meeting Series. pp. 104–105. doi:10.1109/PHOSST.2011.6000067. ISBN 978-1-4244-5730-4. S2CID 9077455.
- Detwiler, Thomas; Stark, Andrew; Basch, Bert; Ralph, Stephen E. (July 2011). "DQPSK for Terabit Ethernet in the 1310 nm band". 2011 IEEE Photonics Society Summer Topical Meeting Series. pp. 143–144. doi:10.1109/PHOSST.2011.6000087. ISBN 978-1-4244-5730-4. S2CID 44199212.
External links
- West, John (April 3, 2009). "Terabit Ethernet on the way". insideHPC.
- Mellor, Chris (February 15, 2009). "Terabit Ethernet possibilities". The Register.
- Wang, Brian (April 24, 2008). "Terabit Ethernet around 2015".
- Duffy, Jim (April 20, 2009). "100 Gigabit Ethernet: Bridge to Terabit Ethernet". Network World. Archived from the original on May 14, 2010.
- Fleishman, Glenn (February 13, 2009). "Terabit Ethernet becomes a photonic possibility". Ars Technica. Condé Nast.
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