Zero ASIC

The architecture is designed to scale almost indefinitely, with 4 e-links allowing multiple chips to be combined in a grid topology, allowing for systems with thousands of cores.

16-core Adapteva Epiphany chip, E16G301, from Parallella single-board computer

On August 19, 2012, Adapteva posted some specifications and information about Epiphany multi-core coprocessors.[6]

In September 2012, a 16-core version, the Epiphany-III (E16G301), was produced using 65 nm[9] (11.5 mm², 500 MHz chip[10]) and engineering samples of 64-core Epiphany-IV (E64G401) were produced using 28 nm GlobalFoundries process (800 MHz).[11]

The primary markets for the Epiphany multi-core architecture include:

• Smartphone applications such as real-time facial recognition, speech recognition, translation, and augmented reality.
• Next generation supercomputers requiring drastically better energy efficiency to allow systems to scale to exaflop computing levels.
• Floating-point acceleration in embedded systems based on field-programmable gate array architectures.

Parallella single-board computer with 16-core Epiphany chip and Zynq-7010 FPGA

In September 2012, Adapteva started project Parallella on Kickstarter, which was marketed as "A Supercomputer for everyone." Architecture reference manuals for the platform were published as part of the campaign to attract attention to the project.[12] The US$750,000 funding goal was reached in a month, with a minimum contribution of US$99 entitling backers to obtain one device; although the initial deadline was set for May 2013, the first single-board computers with 16-core Epiphany chip were finally shipped in December 2013.[13]

Size of board is planned to be 86 mm × 53 mm (3.4 in × 2.1 in).[14][15][16]

The Kickstarter campaign raised US$898,921.[17][18] Raising US$3 million goal was unsuccessful, so no 64-core version of Parallella will be mass-produced.[19] Kickstarter users having donated more than US$750 will get "parallella-64" variant with 64-core coprocessor (made from initial prototype manufacturing with 50 chips yield per wafer).[20]

By 2016, the firm had taped out a 1024-core 64-bit variant of their Epiphany architecture that featured: larger local stores (64 KB), 64-bit addressing, double-precision floating-point arithmetic or SIMD single-precision, and 64-bit integer instructions, implemented in the 16 nm process node.[21] This design included instruction set enhancements aimed at deep-learning and cryptography applications. In July 2017, Adapteva's founder became a DARPA MTO program manager[22] and announced that the Epiphany V was "unlikely" to become available as a commercial product.[23]

The 16-core Parallella achieves roughly 5.0 GFLOPS/W, and the 64-core Epiphany-IV made with 28 nm estimated as 50 GFLOPS/W (single-precision),[24] and 32-board system based on them achieves 15 GFLOPS/W.[25] For comparison, top GPUs from AMD and Nvidia reached 10 GFLOPS/W for single-precision in 2009–2011 timeframe.[26]