Chen–Ho encoding

In what appears to have been a multiple discovery, some of the concepts behind what later became known as Chen–Ho encoding were independently developed by Theodore M. Hertz in 1969[2] and by Tien Chi Chen (陳天機) (1928–)[3][4][5][6] in 1971.

Hertz of Rockwell filed a patent for his encoding in 1969, which was granted in 1971.[2]

Chen first discussed his ideas with Irving Tze Ho (何宜慈) (1921–2003)[7][8][9][10] in 1971. Chen and Ho were both working for IBM at the time, albeit in different locations.[11][12] Chen also consulted with Frank Chin Tung[13] to verify the results of his theories independently.[12] IBM filed a patent in their name in 1973, which was granted in 1974.[14] At least by 1973, Hertz's earlier work must have been known to them, as the patent cites his patent as prior art.[14]

With input from Joseph D. Rutledge and John C. McPherson,[15] the final version of the Chen–Ho encoding was circulated inside IBM in 1974[16] and published in 1975 in the journal Communications of the ACM.[15][17] This version included several refinements, primarily related to the application of the encoding system. It constitutes a Huffman-like prefix code.

The encoding was referred to as Chen and Ho's scheme in 1975,[18] Chen's encoding in 1982[19] and became known as Chen–Ho encoding or Chen–Ho algorithm since 2000.[17] After having filed a patent for it in 2001,[20] Michael F. Cowlishaw published a further refinement of Chen–Ho encoding known as densely packed decimal (DPD) encoding in IEE Proceedings – Computers and Digital Techniques in 2002.[21][22] DPD has subsequently been adopted as the decimal encoding used in the IEEE 754-2008 and ISO/IEC/IEEE 60559:2011 floating-point standards.

Chen noted that the digits zero through seven were simply encoded using three binary digits of the corresponding octal group. He also postulated that one could use a flag to identify a different encoding for the digits eight and nine, which would be encoded using a single bit.

In practice, a series of Boolean transformations are applied to the stream of input bits, compressing BCD encoded digits from 12 bits per three digits to 10 bits per three digits. Reversed transformations are used to decode the resulting coded stream to BCD. Equivalent results can also be achieved by the use of a look-up table.

Chen–Ho encoding is limited to encoding sets of three decimal digits into groups of 10 bits (so called declets).[1] Of the 1024 states possible by using 10 bits, it leaves only 24 states unused[1] (with don't care bits typically set to 0 on write and ignored on read). With only 2.34% wastage it gives a 20% more efficient encoding than BCD with one digit in 4 bits.[12][17]

Both, Hertz and Chen also proposed similar, but less efficient, encoding schemes to compress sets of two decimal digits (requiring 8 bits in BCD) into groups of 7 bits.[2][12]

Larger sets of decimal digits could be divided into three- and two-digit groups.[2]

The patents also discuss the possibility to adapt the scheme to digits encoded in any other decimal codes than 8-4-2-1 BCD,[2] like f.e. Excess-3,[2] Excess-6, Jump-at-2, Jump-at-8, Gray, Glixon, O'Brien type-I and Gray–Stibitz code.[lower-alpha 1] The same principles could also be applied to other bases.

In 1973, some form of Chen–Ho encoding appears to have been utilized in the address conversion hardware of the optional IBM 7070/7074 emulation feature for the IBM System/370 Model 165 and 370 Model 168 computers.[23][24]

One prominent application uses a 128-bit register to store 33 decimal digits with a three digit exponent, effectively not less than what could be achieved using binary encoding (whereas BCD encoding would need 144 bits to store the same number of digits).

• Binary-coded decimal (BCD)
• Densely packed decimal (DPD)
• DEC RADIX 50 / MOD40
• IBM SQUOZE
• Packed BCD
• Unicode transformation format (UTF) (similar encoding scheme)
• Length-limited Huffman code

• Bonten, Jo H. M. (2009-10-06) [2006-10-05]. "Packed Decimal Encoding IEEE-754-2008". Geldrop, Netherlands. Archived from the original on 2018-07-11. Retrieved 2018-07-11.
• Savard, John J. G. (2018) [2001]. "Base-26 Armor". quadibloc. Archived from the original on 2018-07-21. Retrieved 2018-07-21.
• Rinaldi, Russell G.; Moore, Brian B. (1967-03-21) [1964-06-30]. Written at Poughkeepsie & New Paltz, New York, USA. "Data compression/expansion and compressed data processing" (Patent). New York, USA: International Business Machines Corporation (IBM). US Patent US3310786A. Retrieved 2018-07-18 (60 pages) , Rinaldi, Russell G.; Moore, Brian B. (1969-05-20) [1967-01-19, 1964-06-30]. Written at Poughkeepsie & New Paltz, New York, USA. "Serial digital adder employing a compressed data format" (Patent). New York, USA: International Business Machines Corporation (IBM). US Patent US3445641A. Retrieved 2018-07-18 (40 pages) and Rinaldi, Russell G.; Moore, Brian B. (1969-03-11) [1967-01-19, 1964-06-30]. Written at Poughkeepsie & New Paltz, New York, USA. "Data compression/expansion and compressed data processing" (Patent). New York, USA: International Business Machines Corporation (IBM). US Patent US3432811A. Retrieved 2018-07-18. (11 pages) (NB. Three expired patents cited in both, the Hertz and Chen–Ho patents.)
• Bender, Richard R.; Galage, Dominick J. (August 1961). "Packing Mode Control". IBM Technical Disclosure Bulletin. 4 (3): 61–63.
• Tilem, J. Y. (December 1962). "Data Packing and Unpacking Means". IBM Technical Disclosure Bulletin. 5 (7): 48–49.
• Lengyel, E. J.; McMahon, R. F. (March 1967). "Direct Decimal to Binary Address Generator For Small Memories". IBM Technical Disclosure Bulletin. 9 (10): 1347. Retrieved 2020-06-03.