DOME project

The design of computers has changed dramatically in the last decades but the old paradigms still reign. Current designs stem from single computers working on small data sets in one location. SKA will face a completely different landscape, working on an extremely large data set, collected on myriad of geographically separated locations using tens of thousands of separate computers in real time. The fundamental principles for designing such a machine will have to be reexamined. Parameters concerning power envelope, accelerator technologies, workload distribution, memory size, CPU architecture, node intercommunications, must be investigated to draw new baseline to design from.[5] The tools that result from this project are being open-sourced early 2018.

This fundamental research will work as the umbrella for the other six focus areas, help making proper decisions regarding architectural directions.

A first step will be a retrospective analysis of the design of the LOFAR and MeerKAT telescopes and development of a design tool to use when designing very large and distributed computers.

This project will focus on the very large amount of data the DOME must handle. SKA will generates petabytes of data daily and this must be handled differently according to urgency and geographical location whether its near the telescope arrays or in the datacenters. A complex tiered solution must be devised using a lot of technologies that currently is beyond the state of the art. Driving forces behind the designs will be lowest possible cost, accessibility and energy efficiency.

This multi-tier approach will combine several different kinds of software technologies to analyze, sift, distribute, store and retrieve data on hardware ranging from traditional storage media like magnetic tape and hard drives to newly developed technologies like phase-change memory. The suitability of different storage media heavily depends on the usage patterns when writing and reading data, and these patterns will change over time, so there must also be room for changes to the designs.[6]

Transport of data is a major factor, influencing design on the largest scales to the smallest of DOME. The cost of communicating electrically on copper wires will drive the application of low-power photonic interconnects, from connections between collecting antennas and datacenters to connecting devices inside the computers. Both IBM and ASTRON have advanced research programs into nano photonics, beamforming and optical links and they will combine their efforts for the new designs.[7]

This research project is divided into four R&D sections, investigating digital optical interconnects, analog optical interconnects and analog optical signal processing.

1. Digital optical interconnect technology for astronomy signal processing boards.
2. Analog optical interconnection technology for focal-plane array front-ends.
3. Analog optical interconnection technology for photonic phased array receiver tiles.
4. Analog optical interconnection and signal processing technology for photonic focal plane arrays.

In February 2013 at the International Solid-State Circuits Conference (ISSCC), IBM and École Polytechnique Fédérale de Lausanne (EPFL) in Switzerland showed a 100 Gbit/s analog-to-digital converter (ADC).[8] In February 2014 at ISSCC, IBM and ASTRON demoed a 400 Gbit/s ADC.[9]

In 2012 a team at IBM led by Ronald P. Luijten started pursuing a computational dense, and energy efficient 64-bit compute server design based on commodity components, running Linux. A system-on-chip (SoC) design where most necessary components would fit on a single chip would fit these goals best, and a definition of "microserver" emerged where essentially a complete motherboard (except RAM and boot flash) would fit on chip. ARM, x86 and Power ISA based solutions were investigated and a solution based on Freescale's Power ISA-based dual core P5020 / quad core P5040 processor came out on top.

Traditional high performance processors hit a performance wall during the late 2000s when clock-speeds couldn't be increased anymore due to increasing power requirements. One of the solutions is to include hardware to off load the most common and/or compute intensive tasks to specialized hardware called accelerators. This research area will try to identify these areas and design algorithms and hardware to overcome the bottlenecks. There will probably be accelerators doing pattern detection, parsing, data lookup and signal processing. The hardware will be of two classes; fixed accelerators for static tasks, or programmable accelerators for a family of tasks with similar characteristics. The project will also look att massively parallel computing using commodity graphics processors.[10]

The compressive sampling project is fundamental research into signal processing in collabrotation with Delft University of Technology. In the context of radio astronomy capture, analysis and processing of signals is extremely compute intensive on enormous datasets. The goal is to do sampling and compression simultaneously and use machine learning to detect what to keep and what to throw away, preferably as close to the data collectors as possible. This project's goal is to develop compressive sampling algorithms to use in capturing the signal and to calibrate the patterns to keep, in an ever-increasing number of pattern clusters. The research will also tackle the problem of degraded pattern quality, outlier detection, object classification and image formation.[11][12]

Moving data from the collectors to the process facilities are traditionally bogged down due to high latency I/O, low bandwidth connections and data is often multiplied along the way due to lack of purposeful design of the communication network. This research project will try to reduce latency to a minimum and design the I/O systems so data will be written directly into the processing engines on an exascale computer design. The first phase will identify system bottlenecks, and investigate Remote direct memory access (RDMA). The second phase will investigate using standard RDMA technology onto interconnect networking. Phase three includes development of functional prototypes.[13]