David August (computer scientist)

David I. August (born November 27, 1970) is a professor of computer science at Princeton University specializing in compilers and computer architecture. August is a strong advocate of alternatives to parallel programming to address the software impact of multi-core computing.

David I. August
BornNovember 27, 1970
CitizenshipAmerican
EducationElectrical Engineering
Computer Science
Alma materUniversity of Illinois at Urbana-Champaign
Rensselaer Polytechnic Institute
Known formulticore compilation
Scientific career
InstitutionsPrinceton University
ThesisSystematic Compilation for Predicated Execution (2000)
Academic advisorsWen-mei Hwu
Websiteaugust.princeton.edu

August was born in Troy, New York and raised in Parsippany-Troy Hills, New Jersey, graduated summa cum laude in electrical engineering from Rensselaer Polytechnic Institute in 1993, and received his PhD in electrical and computer engineering from the University of Illinois at Urbana-Champaign in 2000 under advisor Wen-mei Hwu. His thesis, entitled Systematic Compilation for Predicated Execution, represented a breakthrough in compilers. Specifically, it showed how a compiler could generate efficient code for architectures with branch predication, such as Intel's IA-64.

In 1999, August was selected as one of five new Ph.D.'s to watch by the Chronicle of Higher Education.[1] Since then, he has produced dozens of articles relating to compilers and computer architecture.[2] The IEEE Computer Society's annual "Top Picks from Computer Architecture Conferences" has recognized his work on microprocessor fault tolerance and his work on multi-core computation for relevance and significance to the field.[3][4][5]

In 2012, he testified as an expert witness in the Oracle America, Inc. v. Google, Inc. patent lawsuit on behalf of Google and stated that the Dalvik virtual machine used in Android did not infringe on Oracle's symbolic reference patent.[6]

Awards and honors

August became an IEEE Fellow in 2015 "for contributions to compilers and architectures for multicore and parallel processing systems".[7]

References

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