List of Intel Xeon chipsets

Around the time that the Pentium III processor was introduced, Intel's Xeon line diverged from its line of desktop processors, which at the time was using the Pentium branding.

The divergence was implemented by using different sockets; since then, the sockets for Xeon chips have tended to remain constant across several generations of implementation.

The chipsets contain a 'memory controller hub' and an 'I/O controller hub', which tend to be called 'north bridge' and 'south bridge' respectively. The memory controller hub connects to the processors, memory, high-speed I/O such as PCI Express, and to the I/O controller hub by a proprietary link. The I/O controller hub, on the other hand, connects to lower-speed I/O, such as SATA, PCI, USB, and Ethernet.

P6-based Xeon chipsets

Dual processor P6-based Xeon chipsets

Intel's initial preferred chipset for Pentium III Xeon was the 840.

Product name Codename Processor FSB supported Memory type supported High-speed interfaces provided Preferred IOCH
440GX AGPset Marlinespike 100 One 72-bit-wide channel of SDRAM, with ECC; up to four DIMMs PIIX4E
840 Carmel 100 or 133 Two channels RDRAM, two RIMMs per channel

Four processor P6-based Xeon chipsets

The Pentium III Xeon bus protocol allowed four processors on the same bus, so the 440GX AGPset could be used in four-CPU systems; the limit of 2GB of main memory remained. These support Slot 2.

There was also the 450NX PCIset, which consisted of several chips: a single 82451NX Memory and IO Bridge Controller roughly analogous to the North Bridge, up to two 82454NX PCI Expander Bridges which converted the protocol used by 451NX to two 32-bit PCI33 or one 64-bit PCI33 bus, along with up to two memory cards each equipped with one 82452NX RAS/CAS Generator chip and two 82453NX Data Path Multiplexer chips. It supported PIIX3 and PIIX4E south bridges, and EDO DRAM.

Eight processor P6-based Xeon chipset

In August 1999 Intel began shipping the Profusion PCIset.[1] The chipset was based on technology developed by the Corollary company, which Intel acquired.[2] It supported up to 8 Pentium III Xeon processors on two busses and maintained cache coherency between them.[3][4][5] Profusion supported up to 32 GB of memory. It saw some limited competition from the NEC Aqua II chipset.[6] Another minor player in the eight-way space was Axil Computer's NX801,[2] which was used in an 8-way (two buses) Pentium Pro design, commercialized by Data General as their AV-8600 computer.[7]

NetBurst-based Xeon chipsets

Dual processor NetBurst-based Xeon chipsets

E7500 corresponded to the first Northwood-based Pentium4 Xeons, E7501 is essentially identical but supports faster FSB and memory. The E7320, E7520 and E7525 chipsets correspond to Prescott-based Pentium4 Xeons, and differ mainly in their PCI Express support. These support Socket 604. The Intel 875P chipset was used in some two-socket motherboards for Xeons.[8][9][10][11]

Product name Codename Processor FSB supported Memory type supported High-speed interfaces provided Preferred IOCH
860[12] Colusa 400 MT/s Two channels of ECC RDRAM at 800 or 600 MT/s, up to 3.2 GB/s AGP 4× port and three hub interfaces for two 533 MB/s PCI buses and a 266 MB/s bus to ICH2 ICH2
E7205 Granite Bay 400 or 533 MT/s Two channels of DDR at 100 MHz or 133 MHz AGP 8× port, single 32-bit 33 MHz PCI bus, 266 MHz 8-bit hub interface for ICH4 ICH4
E7210[13] Canterwood-ES 400 MT/s, 533 MT/s or 800 MT/s Two channels of unbuffered ECC and non-ECC DDR DIMMs (registered ECC is not supported) at 133 MHz, 166 MHz or 200 MHz (DDR-266/333/400) 66 MHz CSA interface for Gigabit LAN. MCH is connected to ICH via 66 MHz 8-bit (266 MT/s) Hub Interface v1.5. A 6300ESB ICH provides up to four 32-bit and/or 64-bit PCI-X at 33 or 66 MHz. Intel E7210 is server variant of 875P (Socket 478) without AGP, it can be used in dual Socket 604 configurations.[14] 6300ESB
E7320[15] Lindenhurst VS 800 MHz Two channels of registered DDR-333 or DDR2-400 SDRAM One ×8 PCI Express interface with max. theoretical bandwidth of 4 GB/s, which may be configured as two ×4 PCIe interfaces.[lower-alpha 1] A 6700PXH provides PCI-X 32-bit and/or 64-bit interfaces at 33 MHz, 66 MHz, 100 MHz, and 133 MHz. 6300ESB, or 82801ER (ICH5R)
E7500 Plumas 400 MHz Two channels of ECC DDR SDRAM at 100 MHz (3.2GB/s peak) Three ECC 1GB/s (66 MHz ×8, 16-bit) 'Hub Interface' channels, which connect to 82870P2 chips to provide two 64-bit 66 MHz PCI or PCI-X buses each, plus one ECC 533MB/s (66 MHz ×4) connector for ICH3-S ICH3-S
E7501 533 MHz Two channels of ECC DDR SDRAM at 133 MHz (4.2GB/s peak)
E7505 Placer[16] 533 MHz Two channels of ECC DDR SDRAM at 133 MHz (4.2GB/s peak) AGP 8× port, three ECC 1GB/s (66 MHz ×8, 16-bit) 'Hub Interface' channels, which connect to 82870P2 chips to provide two 64-bit 66 MHz PCI or PCI-X buses each, plus one ECC 533MB/s (66 MHz ×4) connector for ICH4 ICH4
E7520[17] Lindenhurst 800 MHz Two channels of registered DDR-333 or DDR2-400 SDRAM Three ×8 PCI Express interfaces each with max. theoretical bandwidth of 4 GB/s, which may be configured as two ×4 PCIe interfaces. A 6700PXH provides PCI-X 32-bit and/or 64-bit interfaces at 33 MHz, 66 MHz, 100 MHz, and 133 MHz. 6300ESB, or 82801ER (ICH5R)
E7525[18] Tumwater One ×16 and one ×8 PCI Express interface. A 6700PXH can be attached.

Note that the 82870P2 chips of E7500, E7501 and E7505 were initially designed for the Intel 870 chipset for Itanium 2, and that the summary page of the E7320 datasheet incorrectly claims three PCI Express interfaces.

Quad processor NetBurst-based Xeon chipsets

As Intel didn't have a 4P-capable chipset for NetBurst-based Xeons until 2005, for three years ServerWorks GC-HE served as the de facto standard MP chipset, even being used in Intel's own motherboards (SPSH4 and SRSH4).[19]

Product name Codename Processor FSB supported Memory type supported High-speed interfaces provided Preferred IOCH
E8500[20] Twin Castle 667 MHz dual bus DDR-266, DDR-333 or DDR2-400 three ×8 and one ×4 PCI Express interface 82801EB (ICH5), or 82801ER (ICH5R)
E8501[21] 667 and 800 MHz dual bus

Core-based Xeon chipsets

Single processor Core-based Xeon chipsets

3000 and 3010 are an update on the E7230 chipset, codenamed Mukilteo, which has specifications very similar to the 3000 chipset.[22] E7230 was preceded by E7221, which was Intel's first strictly single-socket server chipset.

Product name Codename Processor FSB supported Memory type supported High-speed interfaces provided Preferred IOCH
3000 Mukilteo-2[23][24] 533 or 800 or 1066 MHz Two channels of ECC DDR2-533 or DDR2-667 PCI Express ×8 port, single 32-bit 33 MHz PCI bus, DMI for ICH7 ICH7
3010 Mukilteo-2P PCI Express 1 ×16 or 2 ×8 ports, single 32-bit 33 MHz PCI bus, DMI for ICH7
3200 Bigby-V 800 or 1066 or 1333 MHz Two channels of ECC DDR2-667 or DDR2-800 PCI Express ×8 port, single 32-bit 33 MHz PCI bus, DMI for ICH9 ICH9
3210 Bigby-P PCI Express 1 ×16 or 2 ×8 ports, single 32-bit 33 MHz PCI bus, DMI for ICH9

Dual processor Core-based Xeon chipsets

These chipsets use a 'dual independent bus' design, in which each socket has its own connection to the chipset. These use the LGA 771 socket. The datasheets omit the 667 MT/s FSB support, so 5400 may support it too.

Product name Codename FSB speed Snoop filter[lower-alpha 2] Memory support High-speed interfaces provided Preferred IOCH
5000P Blackford 667, 1066, 1333 Four channels of FB-DIMM at 533 or 667 MHz, up to 64GB Six PCIe ×4 ports, of which two are normally used for communication with IOCH, and a seventh ×4 port only for IOCH. 631xESB or 632xESB
5000Z Two channels of FB-DIMM at 533 or 667 MHz, up to 16GB Four PCIe ×4 ports, of which two are normally used for communication with IOCH, and a fifth ×4 port only for IOCH.
5000V Two PCIe ×4 ports which are normally used for communication with IOCH, and a third ×4 port only for IOCH.
5000X Greencreek A snoop filter comprising about 1MB of SRAM for coverage of 16MB of cache. Four channels of FB-DIMM at 533 or 667 MHz, up to 64GB Six PCIe ×4 ports, of which two are normally used for communication with IOCH and the other four are combined into a ×16 port, and a seventh ×4 port only for IOCH.
5100 San Clemente Two channels of registered ECC DDR2 533 or 667 MT/s, up to 48GB 6 PCIe ×4 ports, plus one ×4 port reserved for IOCH ICH9R
5400 Seaburg 1066, 1333, 1600 A more advanced[25] snoop filter comprising about 1.6MB of SRAM for coverage of 24MB of cache. Four channels of FB-DIMM at 533, 667 or 800 MHz, up to 128GB 9 PCIe ×4 ports, plus one ×4 port reserved for IOCH 631xESB or 632xESB

Four processor Core-based Xeon chipsets

This chipset uses four independent buses, and is used by the Tigerton and Dunnington processors.

Launch name Codename FSB speed Snoop filter[lower-alpha 3] Memory support Fast I/O IOCH
7300[26] Clarksboro 1066 A very sophisticated snoop filter, comprising 4.5MB of SRAM for coverage of 64MB of cache. Four channels of FB-DIMM at 533 or 667 MHz, up to 256GB 7 PCIe ×4 ports, of which two are usually used to connect to the IOCH, plus an 8th ×4 port only for IOCH 631x or 632x

Nehalem-based Xeon chipsets

Single processor Nehalem-based Xeon chipsets

The 3450 chipset is also compatible with an Intel Core i5 or Intel Core i3 processor.

Product name Codename DMI Fast I/O Other features
3400 Ibex Peak 1.0, 100 MHz PCI Express 6 ×1 ports, single 32-bit 33 MHz PCI bus, DMI for processor 8× USB 2.0, 4× SATA, Integrated LAN
3420 Ibex Peak 1.0, 100 MHz PCI Express 8 ×1 ports, single 32-bit 33 MHz PCI bus, DMI for processor 12× USB 2.0, 6× SATA, Integrated LAN
3450 Ibex Peak 1.0, 100 MHz PCI Express 8 ×1 ports, single 32-bit 33 MHz PCI bus, DMI for processor 14× USB 2.0, 6× SATA, Integrated LAN

Dual processor Nehalem-based Xeon chipsets

The Nehalem-based Xeons for dual-socket systems, initially launched as the Xeon 55xx series, feature a very different system structure: the memory controllers are on the CPU, and the CPUs can communicate with one another as peers without going via the chipset. This means that the 5500 and 5520 (initial codename Tylersburg-EP) chipsets are essentially QPI to PCI Express interfaces; the 5520 is more intended for graphical workstations and the 5500 for servers that do not need vast amounts of PCI Express connectivity

Launch name Codename QPI ports QPI speed Fast I/O IOCH Other features
5500 Tylersburg-24S,
Tylersburg-24D[27]		 1,
2		 4.8, 5.86 or 6.4 GT/s 1 ×16 PCIe Gen 2, 2 ×4 PCIe Gen 1 to talk to southbridge ICH10 (ICH9 also possible) Integrated Management Engine with its own 100 Mbit/s Ethernet[28]
5520 Tylersburg-36S,
Tylersburg-36D		 1,
2		 4.8, 5.86 or 6.4 GT/s 2 ×16 PCIe Gen 2, 1 ×4 PCIe Gen 1 to talk to southbridge ICH10 (ICH9 also possible) Integrated Management Engine with its own 100 Mbit/s Ethernet[28]

As well as the 5530

Four processor Nehalem-based Xeon chipsets
Launch name Codename QPI ports QPI speed Fast I/O IOCH Other features
7500 Boxboro 2 6.4 GT/s 2 ×16 PCIe Gen 2, 1 ×4 PCIe Gen 1 to talk to southbridge ICH10 (ICH9 also possible) Integrated Management Engine with its own 100 Mbit Ethernet

Sandy Bridge-based Xeon chipsets

Single processor Sandy Bridge-based Xeon chipsets

The Intel C200 series chipsets that support the Intel Xeon E3-1200 CPU family.[29][30]

Product name Codename DMI Fast I/O Other features
C202 Cougar Point 2.0, 100 MHz PCI Express 8 × 1 ports, single 32-bit 33 MHz PCI bus, DMI for processor 12 × USB 2.0, 6 × SATA 1.5/3 Gbit/s, Integrated LAN
C204 12 × USB 2.0, 2 × SATA 1.5/3/6 Gbit/s + 4 × SATA 1.5/3 Gbit/s, Integrated LAN
C206 14 × USB 2.0, 2 × SATA 1.5/3/6 Gbit/s + 4 × SATA 1.5/3 Gbit/s, Integrated LAN, Integrated Graphics, Intel Anti-Theft Technology, Active Management Technology 7.0

Dual processor Sandy Bridge-based Xeon chipsets

The Intel C600 series chipsets support the Intel Xeon E5-2600 CPU family. Common to all C600 variants are the following features:

  • DMI interface to CPU at 20 GT/s
  • 8 PCIe 2.0 (5 GT/s) lanes, configurable by the board manufacturer as 8×1, 4×2, 2×4, or 1×8.
  • 2 SATA ports supporting 6/3/1.5 gigabaud operation
  • 4 SATA ports supporting 3/1.5 gigabaud operation
  • one PCI 2.3 32-bit 33 MHz bus interface
  • 14 USB 2.0 ports
  • single-port Gigabit Ethernet controller
  • Active Management Technology 7.0 and Anti-Theft Technology
  • HD Audio controller

Some chipset variants have additional mass storage interfaces:

Product name Codename additional mass storage capabilities
C602J Patsburg none
C602 4× SATA 1.5/3 gigabaud ports
C604 4× SAS/SATA 1.5/3 gigabaud ports
C606 8× SAS/SATA 1.5/3 gigabaud ports optionally through dedicated PCIe 2.0 ×4 (5 GT/s) interface, 1 additional SMBus
C608 8× SAS/SATA 1.5/3 gigabaud ports optionally through dedicated PCIe 2.0 ×4 (5 GT/s) interface, 2 additional SMBus

Dual processor Gladden/Sandy Bridge-EP/EN-based Xeon chipsets

The Intel Communications 8900 series chipsets that support the Gladden Intel Xeon E3-11xx[31] or Sandy Bridge-EP/EN Intel Xeon E5-2xxx[32] CPU families.

Product name Codename DMI Fast I/O Other features
DH8900 Cave Creek 2.0, 100 MHz PCI Express 2.0 ×16 + PCI Express 1.0 4 × 1 ports, DMI for processor 6 × USB 2.0, 6 × SATA 1.5/3 Gbit/s, 4 × Integrated LAN
DH8903 PCI Express 2.0 ×8 + PCI Express 1.0 4 × 1 ports, DMI for processor 6 × USB 2.0, 2 × SATA 1.5/3 Gbit/s, 4 × Integrated LAN, 5 Gbit/s QuickAssist
DH8910 PCI Express 2.0 ×4 + PCI Express 1.0 4 × 1 ports, DMI for processor 6 × USB 2.0, 2 × SATA 1.5/3 Gbit/s, 4 × Integrated LAN, 10 Gbit/s QuickAssist
DH8920 PCI Express 2.0 ×4 + PCI Express 1.0 4 × 1 ports, DMI for processor 6 × USB 2.0, 2 × SATA 1.5/3 Gbit/s, 4 × Integrated LAN, 20 Gbit/s QuickAssist

Ivy Bridge-based Xeon chipsets

Single processor Ivy Bridge-based Xeon chipsets

The Intel C200 series chipsets that support the Intel Xeon E3-1200v2 CPU family.[33]

Product name Codename DMI Fast I/O Other features
C216 Panther Point 2.0, 100 MHz PCI Express 2.0 8 × 1 ports, single 32-bit 33 MHz PCI bus, DMI for processor 4 × USB 3.0 + 14 × USB 2.0, 2 × SATA 1.5/3/6 Gbit/s + 4 × SATA 1.5/3 Gbit/s, Integrated LAN, Integrated Graphics, Intel Anti-Theft Technology, Active Management Technology 8.0

Haswell-based Xeon chipsets

Single processor Haswell-based Xeon chipsets

The Intel C220 series chipsets support the Intel Xeon E3-1200v3 CPU family.[34]

Product name Codename DMI Fast I/O Other features
C222 Lynx Point 2.3, 100 MHz Eight PCI Express 2.0 ×1 ports, DMI for processor 10 × USB 2.0/3.0, 2 × SATA 1.5/3/6 Gbit/s + 4 × SATA 1.5/3 Gbit/s, Integrated LAN, Integrated IDE, Rapid Storage Technology enterprise
C224 12 × USB 2.0/3.0, 4 × SATA 1.5/3/6 Gbit/s + 2 × SATA 1.5/3 Gbit/s, Integrated LAN, Integrated IDE, Rapid Storage Technology enterprise
C226 8 × USB 2.0, 6 USB 3.0, 6 × SATA 1.5/3/6 Gbit/s, Integrated LAN, Integrated Graphics, Rapid Storage Technology enterprise, Active Management Technology 9.0, Identity Protection Technology, VGA, Wireless Display

Skylake-based Xeon chipsets

Single processor Skylake-based Xeon chipsets

The Intel C230 series chipsets support the Intel Xeon E3-1200v5 CPU family.

Both, the C232 and the C236 support the LGA 1151 socket.

Product name Codename DMI Fast I/O Other features
C232 Sunrise Point 3.0, 100 MHz Max. 8 lanes PCIe 3.0 at ×4, ×2, ×1 configuration, DMI for processor 6× USB 3.0, 6× USB 2.0, 6× SATA 6 Gbit/s, M.2 & SATA Express support, integrated LAN, Rapid Storage Technology enterprise
C236 Max. 20 lanes PCIe 3.0 at ×4, ×2, ×1 configuration, DMI for processor 10× USB 3.0, 4× USB 2.0, 8× SATA 6 Gbit/s, M.2 & SATA Express support, integrated LAN, Rapid Storage Technology enterprise, 3× displays

Kaby Lake-based Xeon chipsets

Coffee Lake-based Xeon chipsets

The Intel C246 series chipsets support the Intel Xeon E-2100 series of CPUs.[35]

Product name Codename DMI Fast I/O Other features
C242  ? 3.0 ×4 Max. 10 lanes PCIe 3.0 6× USB 3.1 (up to 2× USB 3.1 Gen 2, up to 6× USB 3.1 Gen 1), 6× USB 2.0, SATA, Ethernet, Wifi
C246 Max. 24 lanes PCIe 3.0 10× USB 3.1 (up to 6× USB 3.1 Gen 2, up to 10× USB 3.1 Gen 1), 4× USB 2.0, SATA, Ethernet, Wifi

See also

References
  1. The summary page of the E7320 datasheet incorrectly claims three PCI Express interfaces.
  2. To keep cache coherency traffic between the two sockets from appearing on the second bus.
  3. To keep cache coherency traffic between the two sockets from appearing on the other three buses.
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