Model-specific register

With the introduction of the 80386 processor, Intel began introducing "experimental" features that would not necessarily be present in future versions of the processor. The first of these were two "test registers" (TR6 and TR7) that enabled testing of the processor's translation lookaside buffer (TLB); a special variant of the MOV instruction allowed moving to and from the test registers.[1] Three additional test registers followed in the 80486 (TR3–TR5) that enabled testing of the processor's caches for code and data.[2] None of these five registers were implemented in the subsequent Pentium processor; the special variant of MOV generated an invalid opcode exception.[3][4]

With the introduction of the Pentium processor, Intel provided a pair of instructions (RDMSR and WRMSR) to access current and future "model-specific registers", as well as the CPUID instruction to determine which features are present on a particular model. Many of these registers have proven useful enough to be retained. Intel has classified these as architectural model-specific registers and has committed to their inclusion in future product lines.[5]

Reading and writing to these registers is handled by the rdmsr and wrmsr instructions, respectively. As these are privileged instructions, they can be executed only by the operating system. Use of the Linux msr kernel module creates a pseudo file "/dev/cpu/x/msr" (with a unique x for each processor or processor core). A user with permissions to read and/or write to this file can use the file I/O API to access these registers. The msr-tools[6] package provides a reference implementation.

Documentation regarding which MSRs a certain processor implementation supports is usually found in the processor documentation of the CPU vendor. Examples for rather well-known MSRs are the memory type range registers (MTRRs) and the address-range registers (ARRs).

• LOADALL

• https://www.coreboot.org/Msrtool