555 timer IC

Several books report the name "555" timer IC derived from the three 5 kΩ resistors inside the chip.[10][11][12] However, in a recorded interview with an online transistor museum curator,[13] Hans Camenzind said "It was just arbitrarily chosen. It was Art Fury (marketing manager) who thought the circuit was gonna sell big who picked the name '555' timer IC.."[14]

The internal block diagram and schematic of the 555 timer are highlighted with the same color across all three drawings to clarify how the chip is implemented:[2]

• Voltage divider: Between the positive supply voltage V_CC and the ground GND is a voltage divider consisting of three identical resistors (5 kΩ for bipolar timers, 100 kΩ or higher for CMOS) to create reference voltages for the analog comparators. CONTROL is connected between the upper two resistors, allowing an external voltage to control the reference voltages:
  • When CONTROL is not driven, this divider creates an upper reference voltage of 2⁄3 V_CC and a lower reference voltage of 1⁄3 V_CC.
  • When CONTROL is driven, the upper reference voltage will instead be V_CONTROL and the lower reference voltage will be 1⁄2 V_CONTROL.
• Threshold comparator: The comparator's negative input is connected to voltage divider's upper reference voltage, and the comparator's positive input is connected to THRESHOLD.
• Trigger comparator: The comparator's positive input is connected to voltage divider's lower reference, and the comparator's negative input is connected to TRIGGER.
• Latch: A set-reset latch stores the state of the timer and is controlled by the two comparators. RESET overrides the other two inputs, thus the latch (and therefore the entire timer) can be reset at any time.
• Output: The output of the latch is followed by an output stage with push–pull output drivers that can supply up to 200 mA for bipolar timers, lower for CMOS timers.
• Discharge: Also, the output of the latch controls a transistor acting as an electronic switch that connects DISCHARGE to ground (convenient for discharging a timing capacitor) or leaves it disconnected.

• 
  555 internal block diagram[1]
• 
  555 internal schematic of bipolar version
• 
  555 internal schematic of CMOS version

The pinout of the 8-pin 555 timer[1] and 14-pin 556 dual timer[21] are shown in the following table. Since the 556 is conceptually two 555 timers that share power pins, the pin numbers for each half are split across two columns.[2]

In the following table, longer pin designations are used, because manufacturers never standardized the abbreviated pin names across all datasheets.

• 
  Pinout of 555 single timer.[1][2]
• 
  Pinout of 556 dual timer.[21][2]

Schematic of a 555 timer in astable mode

Waveform in astable mode

In the astable configuration, the 555 timer puts out a continuous stream of rectangular pulses having a specific period.

The astable configuration is implemented using two resistors, ${\displaystyle R_{1}}$ and ${\displaystyle R_{2},}$ and one capacitor ${\displaystyle C}$. The threshold and trigger pins are both connected to the capacitor; thus they have the same voltage.

Its repeated operating cycle (starting with the capacitor uncharged) is:

1. Since the capacitor's voltage will be below 1⁄3 V_CC, the trigger pin causes the 555's internal latch to change state, causing OUT to go high and the internal discharge transistor to cut-off.
2. Since the discharge pin is no longer short-circuited to ground, the capacitor starts charging via current from Vcc through the resistors ${\displaystyle R_{1}}$ and ${\displaystyle R_{2}}$.
3. Once the capacitor charge reaches 2⁄3 Vcc, the threshold pin causes the 555's internal latch to change state, causing OUT to go low and the internal discharge transistor to go into saturation (maximal-conductivity) mode.
4. This discharge transistor provides a discharge path, so the capacitor starts discharging through ${\displaystyle R_{2}}$.
5. Once the capacitor's voltage drops below 1⁄3 V_CC, the cycle repeats from step 1.

During the first pulse, the capacitor charges from 0 V to 2⁄3 V_CC, however, in later pulses, it only charges from 1⁄3 V_CC to 2⁄3 V_CC. Consequently, the first pulse has a longer high time interval compared to later pulses. Moreover, the capacitor charges through both resistors but only discharges through ${\displaystyle R_{2}}$, thus the output high interval is longer than the low interval. This is shown in the following equations:

The output high time interval of each pulse is given by:[16]

${\displaystyle t_{\text{high}}=\ln(2)\cdot (R_{1}+R_{2})\cdot C}$

The output low time interval of each pulse is given by:[16]

${\displaystyle t_{\text{low}}=\ln(2)\cdot R_{2}\cdot C}$

Hence, the frequency ${\displaystyle f}$ of the pulse is given by:[16]

${\displaystyle f={\frac {1}{t_{\text{high}}+t_{\text{low}}}}={\frac {1}{\ln(2)\cdot (R_{1}+2\,R_{2})\cdot C}}}$

and the duty cycle ${\displaystyle D}$ is given by:[16]

${\displaystyle D~(\%)={\frac {t_{\text{high}}}{t_{\text{high}}+t_{\text{low}}}}\cdot 100={\frac {R_{1}+R_{2}}{R_{1}+2\,R_{2}}}\cdot 100}$

where ${\displaystyle t}$ is the time in seconds, ${\displaystyle R}$ is the resistance in ohms, ${\displaystyle C}$ is the capacitance in farads, and ${\displaystyle \ln(2)}$ is the natural logarithm of 2[lower-alpha 1].

Schematic of a 555 timer in astable mode with a 1N4148 diode to create a duty cycles less than 50%

Resistor ${\displaystyle R_{1}}$ requirements:

• The maximum power rating of ${\displaystyle R_{1}}$ must be greater than ${\displaystyle {\frac {{V_{\text{CC}}}^{2}}{R_{1}}}}$, per Ohm's law.
• Particularly with bipolar 555 types, low values of ${\displaystyle R_{1}}$ must be avoided so that the output stays saturated near zero volts during discharge, as assumed by the above equation. Otherwise, the output low time will be greater than calculated above.

To create an output high time shorter than the low time (i.e., a duty cycle less than 50%) a fast diode (i.e. 1N4148 signal diode) can be placed in parallel with R₂, with the cathode on the capacitor side.[16] This bypasses R₂ during the high part of the cycle, so that the high interval depends only on R₁ and C, with an adjustment based on the voltage drop across the diode. The low time is unaffected by the diode and so remains ${\textstyle \ln(2)\,R_{2}\,C\,.}$ But the diode's forward voltage drop V_diode slows charging on the capacitor, so the high time is longer than the often-cited ${\textstyle \ln(2)\,R_{1}\,C}$ to become:

${\displaystyle t_{\text{high}}=\ln \left({\frac {2\,V_{\text{CC}}-3\,V_{\text{diode}}}{V_{\text{CC}}-3\,V_{\text{diode}}}}\right)\cdot R_{1}\cdot C,}$

where V_diode is when the diode's "on" current is 1⁄2 of V_CC/R₁ (which depends on the type of diode and can be found in datasheets or measured). When V_diode is small relative to V_cc, this charging is faster and approaches ${\textstyle \ln(2)\,R_{1}\,C}$ but is slower the closer V_diode is to V_cc:

As an extreme example, when V_CC = 5 V, and V_diode = 0.7 V, high time is 1.00 R₁C, which is 45% longer than the "expected" 0.693 R₁C. At the other extreme, when V_cc = 15 V, and V_diode = 0.3 V, the high time is 0.725 R₁C, which is closer to the expected 0.693 R₁C. The equation approaches 0.693 R₁C as V_diode approaches 0 V.

In the previous example schematics, the control pin was not used, thus it should connected to ground through a 10 nF decoupling capacitor to shunt electrical noise. However if a time-varying voltage source was applied to the control pin, then the pulse widths would be dependent on the control voltage.

Schematic of a 555 in monostable mode. Example values C = 100 nF, R = 180 kΩ to 220 kΩ for debouncing a pulled-up pushbutton.

Waveform in monostable mode

Monostable mode produces an output pulse when the trigger signals drops below 1⁄3 V_CC. An RC circuit sets the output pulse's duration as the time ${\displaystyle t}$ in seconds it takes to charge C to 2⁄3 V_CC:[16]

${\displaystyle t=\ln(3)\cdot R\cdot C,}$

where ${\displaystyle R}$ is the resistance in ohms, ${\displaystyle C}$ is the capacitance in farads, ${\displaystyle \ln(3)}$ is the natural log of 3 constant[lower-alpha 2]. The output pulse duration can be lengthened or shortened as desired by adjusting the values of R and C. Subsequent triggering before the end of this timing interval won't affect the output pulse.[25]

After the timing interval completes, the capacitor is almost instantly discharged through the Discharge pin, to then allow for subsequent triggering.

The table of common values (right) are solutions to that timing equation.

Scaling R and C by opposite powers of 10 will provide the same timing. For instance, ~1 ms results from either:

• 1 nF and 910 kΩ,
• 10 nF and 91 kΩ (values from table), or
• 100 nF and 9.1 kΩ.

For each row in the example table (right), two additional timing values can easily be created by adding a second resistor in parallel or series. In parallel, the new timing is half the table time. In series, the new timing is double the table time.

• 5 ms ≅ 100 nF and 45.5 kΩ (two 91 kΩ resistors in parallel)
• 10 ms ≅ 100 nF and 91 kΩ (values from table)
• 20 ms ≅ 100 nF and 182 kΩ (two 91 kΩ resistors in series)

Schematic of a 555 in bistable SR latch mode.

Active-low SR latch symbol.

A 555 timer can act as an active-low SR latch (though without an inverted Q output) by connecting a Reset input signal to the RESET pin and connecting a Set input signal to the TR pin. Thus, pulling Set momentarily low acts as a "set" and transitions the output to the high state (V_CC). Conversely, pulling Reset momentarily low acts as a "reset" and transitions the Out pin to the low state (GND).

No timing capacitors are required in a bistable configuration. The threshold input is grounded because it is unused.[26] The trigger and reset inputs may be held high via pull-up resistors if they are normally Hi-Z and only enabled by connecting to ground. The discharge pin isn't needed in this configuration, though it can be optionally used as an open-collector output.

Schematic of a 555 timer in bistable Schmitt trigger inverter mode. Example values C = 100 nF, R1 & R2 = 100 kΩ.

Schmitt trigger inverter symbol.

A 555 timer can be used to create a Schmitt trigger inverter gate, which converts a noisy input into a clean digital output.

An input signal is AC-coupled through a low value series capacitor, then biased by identical high-resistance resistors ${\displaystyle R_{1}}$ and ${\displaystyle R_{2}}$, which causes the signal to be centered at half V_cc. This centered signal is connected to both the trigger and threshold input pins of the timer. The input signal must be strong enough to excite the trigger levels of the comparators to exceed 1⁄3 V_CC and 2⁄3 V_CC in order to cause them to change state.[27] The discharge pin isn't needed in this configuration, though it can be optionally used as an open-collector output.

Die of a NE556 dual timer manufactured by STMicroelectronics

Pinout of 556 dual timer[21][16]

The dual version is called 556. It features two complete 555 timers in a 14-pin package; only the two power-supply pins are shared between the two timers.[21][16] In 2020, the bipolar version was available as the NE556,[21] and the CMOS versions were available as the Intersil ICM7556 and Texas Instruments TLC556 and TLC552. See derivatives table in this article.[17][39][38]

Die of a NE558 quad timer manufactured by Signetics

Pinout of 558 quad timer[2]

558 internal block diagram. It is different from 555 and 556 timers.[2]

The quad version is called 558 and has four reduced-functionality timers in a 16-pin package designed primarily for monostable multivibrator applications.[49][2] By 2014, many versions of 16-pin NE558 have become obsolete.[50]

Partial list of differences between 558 and 555 chips:[2][50]

• One V_CC and one GND, similar to 556 chip.
• Four "Reset" are tied together internally to one external pin (558).
• Four "Control Voltage" are tied together internally to one external pin (558).
• Four "Triggers" are falling-edge sensitive (558), instead of level sensitive (555).
• Two resistors in the voltage divider (558), instead of three resistors (555).
• One comparator (558), instead of two comparators (555).
• Four "Output" are open-collector (O.C.) type (558), instead of push–pull (P.P.) type (555).