Plurality (company)
Plurality Ltd. is an Israeli semiconductor company, the developer of the HyperCore technology and the HAL (HyperCore Architecture Line) multi-core processor. The company is a member of the Multicore Association.[2]
 | |
| Type | Private |
|---|---|
| Industry | Semiconductors |
| Founded | 2004[1] |
| Headquarters | Israel |
| Products | Multi-core |
| Website | Plurality.com |
HyperCore
Plurality develops the HyperCore CPU technology, which is a MIMD 32-bit RISC based multi-processor on a single chip,[3] and contains from 16 to 256 cores.[4] HyperCore technology supports executing both fine-grained and coarse-grain parallelism due to its special hardware Synchronizer/Scheduler, shared memory and task based programming model.
The HyperCore technology's synchronizer/scheduler (patented,[5] see below also) eliminates the need of repeatedly executing a special kernel program controlling and deciding which task (or thread) to currently assign and execute on a given processor. The ability to synchronize tasks in hardware allows the processor to support fine-grained programs and to achieve almost a linear speedup. Fine grained programs can only be executed when tasks' duration is significantly shorter than the overhead time introduced by the scheduler. The HyperCore's shared memory (patent pending) avoid the coherency problem and keep a single memory space for all cores in the system thus simplifying the programming model significantly.
Patents
Synchronizer/scheduler
Dr. Nimrod Bayer and Dr. Ran Ginosar, two of Plurality's founders, received United States Patent 5202987 (“A High Flow-Rate Synchronizer/Scheduler for Multiprocessors”) for the company's core technology on April 13, 1993. The patent has been cited by more than 30 subsequent patents. The patent abstract is as follows:
"A high flow rate synchronizer/scheduler apparatus for a multiprocessor system during program run-time, comprises a connection matrix for monitoring and detecting computational tasks which are allowed for execution containing a task map and a network of nodes for distributing to the processors information or computational tasks detected to be enabled by the connection matrix. The network of nodes possesses the capability of decomposing information on a pack of allocated computational tasks into messages of finer sub-packs to be sent towards the processors, as well as the capability of unifying packs of information on termination of computational tasks into a more comprehensive pack. A method of performing the synchronization/scheduling in the multiprocessor system of this apparatus is also described."