Non-return-to-zero

Unipolar NRZ(L), or unipolar non-return-to-zero level

"One" is represented by a DC bias on the transmission line (conventionally positive), while "zero" is represented by the absence of bias – the line at 0 volts or grounded. For this reason it is also known as "on-off keying". In clock language, a "one" transitions to or remains at a biased level on the trailing clock edge of the previous bit, while "zero" transitions to or remains at no bias on the trailing clock edge of the previous bit. Among the disadvantages of unipolar NRZ is that it allows for long series without change, which makes synchronization difficult, although this is not unique to the unipolar case. One solution is to not send bytes without transitions. More critically, and unique to unipolar NRZ, are issues related to the presence of a transmitted DC level – the power spectrum of the transmitted signal does not approach zero at zero frequency. This leads to two significant problems: first, the transmitted DC power leads to higher power losses than other encodings, and second, the presence of a DC signal component requires that the transmission line be DC-coupled.

"One" is represented by one physical level (usually a positive voltage), while "zero" is represented by another level (usually a negative voltage). In clock language, in bipolar NRZ-level the voltage "swings" from positive to negative on the trailing edge of the previous bit clock cycle.

An example of this is RS-232, where "one" is −12 V to −5 V and "zero" is +5 V to +12 V.

Non-return-to-zero space

Encoder for NRZS, toggle on zero

"One" is represented by no change in physical level, while "zero" is represented by a change in physical level. In clock language, the level transitions on the trailing clock edge of the previous bit to represent a "zero".

This "change-on-zero" is used by High-Level Data Link Control and USB. They both avoid long periods of no transitions (even when the data contains long sequences of 1 bits) by using zero-bit insertion. HDLC transmitters insert a 0 bit after 5 contiguous 1 bits (except when transmitting the frame delimiter "01111110"). USB transmitters insert a 0 bit after 6 consecutive 1 bits. The receiver at the far end uses every transition — both from 0 bits in the data and these extra non-data 0 bits — to maintain clock synchronization. The receiver otherwise ignores these non-data 0 bits.

An example of the NRZI encoding, transition on 1

The opposite convention, transition on 0

Encoder for NRZI, toggle on one

Non-return-to-zero, inverted (NRZI, also known as non-return to zero IBM,[1] inhibit code,[2] or IBM code[2]) was devised by Bryon E. Phelps (IBM) in 1956.[2][3] It is a method of mapping a binary signal to a physical signal for transmission over some transmission medium. The two-level NRZI signal distinguishes data bits by the presence or absence of a transition at a clock boundary. The NRZI encoded signal can be decoded unambiguously after passing through a data path that doesn’t preserve polarity.

Which bit value corresponds to a transition varies in practice, NRZI applies equally to both. NRZI-M, non-return zero inverted mark, adopts the convention that a logical 1 is encoded as a transition, and a logical 0 is encoded as no transition. The HDLC and Universal Serial Bus protocols use the opposite convention: NRZI-S, non-return zero inverted space, which encodes a logical 0 as a transition, and a logical 1 as no transition. Neither NRZI encoding guarantees that the encoded bitstream has transitions.

An asynchronous receiver uses an independent bit clock that is phase synchronized by detecting bit transitions. When an asynchronous receiver decodes a block of bits without a transition longer than the period of the difference between the frequency of the transmitting and receiving bit clocks, the decoder’s bit clock is either 1 bit earlier than the encoder resulting in a duplicated bit being inserted in the decoded data stream, or the decoder’s bit clock is 1 bit later than the encoder resulting in a duplicated bit being removed from the decoded data stream. Both are referred to as “bit slip” denoting that the phase of the bit clock has slipped a bit period.

Forcing transitions at intervals shorter than the bit clock difference period allows an asynchronous receiver to be used for NRZI bit streams. Additional transitions necessarily consume some of the data channel’s rate capacity. Consuming no more of the channel capacity than necessary to maintain bit clock synchronization without increasing costs related to complexity is a problem with many possible solutions.

Run-length limited (RLL) encodings have been used for magnetic disk and tape storage devices using fixed-rate RLL codes that increase the channel data rate by a known fraction of the information data rate. HDLC and USB use bit stuffing: inserting an additional 0 bit before NRZI-S encoding to force a transition in the encoded data sequence after 5 (HLDC) or 6 (USB) consecutive 1 bits. Bit stuffing is more efficient, consuming channel capacity only when necessary but results in a variable information data rate because it takes more channel data bits to send a long string of marks (1’s) with inserted 0’s to force a transition to be encoded than to send a long string of spaces (0’s) that encode as transitions.

Synchronized NRZI (SNRZI) and group-coded recording (GCR) are modified forms of NRZI.[4] In SNRZI-M each 8-bit group is extended to 9 bits by a 1 in order to insert a transition for synchronisation.[4]