Power MOSFET

Fig.2: Contribution of the different parts of the MOSFET to the on-state resistance.

When the power MOSFET is in the on-state (see MOSFET for a discussion on operation modes), it exhibits a resistive behaviour between the drain and source terminals. It can be seen in figure 2 that this resistance (called R_DSon for "drain to source resistance in on-state") is the sum of many elementary contributions:

• R_S is the source resistance. It represents all resistances between the source terminal of the package to the channel of the MOSFET: resistance of the wire bonds, of the source metallisation, and of the N⁺ wells;
• R_ch. This is the channel resistance. It is inversely proportional to the channel width, and for a given die size, to the channel density. The channel resistance is one of the main contributors to the R_DSon of low-voltage MOSFETs, and intensive work has been carried out to reduce their cell size in order to increase the channel density;
• R_a is the access resistance. It represents the resistance of the epitaxial zone directly under the gate electrode, where the direction of the current changes from horizontal (in the channel) to vertical (to the drain contact);
• R_JFET is the detrimental effect of the cell size reduction mentioned above: the P implantations (see figure 1) form the gates of a parasitic JFET transistor that tend to reduce the width of the current flow;
• R_n is the resistance of the epitaxial layer. As the role of this layer is to sustain the blocking voltage, R_n is directly related to the voltage rating of the device. A high voltage MOSFET requires a thick, low-doped layer, i.e., highly resistive, whereas a low-voltage transistor only requires a thin layer with a higher doping level, i.e., less resistive. As a result, R_n is the main factor responsible for the resistance of high-voltage MOSFETs;
• R_D is the equivalent of R_S for the drain. It represents the resistance of the transistor substrate (the cross section in figure 1 is not at scale, the bottom N⁺ layer is actually the thickest) and of the package connections.

Fig. 3: The R_DSon of the MOSFETs increase with their voltage rating.

When in the OFF-state, the power MOSFET is equivalent to a PIN diode (constituted by the P⁺ diffusion, the N⁻ epitaxial layer and the N⁺ substrate). When this highly non-symmetrical structure is reverse-biased, the space-charge region extends principally on the light-doped side, i.e., over the N⁻ layer. This means that this layer has to withstand most of the MOSFET's OFF-state drain-to-source voltage.

However, when the MOSFET is in the ON-state, this N⁻ layer has no function. Furthermore, as it is a lightly doped region, its intrinsic resistivity is non-negligible and adds to the MOSFET's ON-state Drain-to-Source Resistance (R_DSon) (this is the R_n resistance in figure 2).

Two main parameters govern both the breakdown voltage and the R_DSon of the transistor: the doping level and the thickness of the N⁻ epitaxial layer. The thicker the layer and the lower its doping level, the higher the breakdown voltage. On the contrary, the thinner the layer and the higher the doping level, the lower the R_DSon (and therefore the lower the conduction losses of the MOSFET). Therefore, it can be seen that there is a trade-off in the design of a MOSFET, between its voltage rating and its ON-state resistance. This is demonstrated by the plot in figure 3.

It can be seen in figure 1 that the source metallization connects both the N⁺ and P⁺ implantations, although the operating principle of the MOSFET only requires the source to be connected to the N⁺ zone. However, if it were, this would result in a floating P zone between the N-doped source and drain, which is equivalent to a NPN transistor with a non-connected base. Under certain conditions (under high drain current, when the on-state drain to source voltage is in the order of some volts), this parasitic NPN transistor would be triggered, making the MOSFET uncontrollable. The connection of the P implantation to the source metallization shorts the base of the parasitic transistor to its emitter (the source of the MOSFET) and thus prevents spurious latching. This solution, however, creates a diode between the drain (cathode) and the source (anode) of the MOSFET, making it able to block current in only one direction.

Body diodes may be utilized as freewheeling diodes for inductive loads in configurations such as H bridge or half bridge. While these diodes usually have rather high forward voltage drop, they can handle large currents and are sufficient in many applications, reducing part count, and thus, device cost and board space. To increase efficiency, synchronous rectification is often used to minimize the amount of time that the body diode conducts current.

In the MOSFET datasheets, the capacitances are often named C_iss (input capacitance, drain and source terminal shorted), C_oss (output capacitance, gate and source shorted), and C_rss (reverse transfer capacitance, source connected to ground). The relationship between these capacitances and those described below is:

$${\displaystyle {\begin{matrix}C_{iss}&=&C_{GS}+C_{GD}\\C_{oss}&=&C_{GD}+C_{DS}\\C_{rss}&=&C_{GD}\end{matrix}}}$$

Where C_GS, C_GD and C_DS are respectively the gate-to-source, gate-to-drain and drain-to-source capacitances (see below). Manufacturers prefer to quote C_iss, C_oss and C_rss because they can be directly measured on the transistor. However, as C_GS, C_GD and C_DS are closer to the physical meaning, they will be used in the remaining of this article.

The C_GS capacitance is constituted by the parallel connection of C_oxN+, C_oxP and C_oxm (see figure 4). As the N⁺ and P regions are highly doped, the two former capacitances can be considered as constant. C_oxm is the capacitance between the (polysilicon) gate and the (metal) source electrode, so it is also constant. Therefore, it is common practice to consider C_GS as a constant capacitance, i.e. its value does not depend on the transistor state.

The C_GD capacitance can be seen as the connection in series of two elementary capacitances. The first one is the oxide capacitance (C_oxD), constituted by the gate electrode, the silicon dioxide and the top of the N epitaxial layer. It has a constant value. The second capacitance (C_GDj) is caused by the extension of the space-charge zone when the MOSFET is in off-state. Therefore, it is dependent upon the drain to gate voltage. From this, the value of C_GD is:

$${\displaystyle C_{GD}={\frac {C_{oxD}\times C_{GDj}\left(V_{GD}\right)}{C_{oxD}+C_{GDj}\left(V_{GD}\right)}}}$$

The width of the space-charge region is given by[33]

$${\displaystyle w_{GDj}={\sqrt {\frac {2\epsilon _{Si}V_{GD}}{qN}}}}$$

where ${\displaystyle \epsilon _{Si}}$ is the permittivity of the Silicon, q is the electron charge, and N is the doping level. The value of C_GDj can be approximated using the expression of the plane capacitor:

$${\displaystyle C_{GDj}=A_{GD}{\frac {\epsilon _{Si}}{w_{GDj}}}}$$

Where A_GD is the surface area of the gate-drain overlap. Therefore, it comes:

$${\displaystyle C_{GDj}\left(V_{GD}\right)=A_{GD}{\sqrt {\frac {q\epsilon _{Si}N}{2V_{GD}}}}}$$

It can be seen that C_GDj (and thus C_GD) is a capacitance whose value is dependent upon the gate to drain voltage. As this voltage increases, the capacitance decreases. When the MOSFET is in on-state, C_GDj is shunted, so the gate to drain capacitance remains equal to C_oxD, a constant value.

As the source metallization overlaps the P-wells (see figure 1), the drain and source terminals are separated by a P-N junction. Therefore, C_DS is the junction capacitance. This is a non-linear capacitance, and its value can be calculated using the same equation as for C_GDj.

To operate, the MOSFET must be connected to the external circuit, most of the time using wire bonding (although alternative techniques are investigated). These connections exhibit a parasitic inductance, which is in no way specific to the MOSFET technology, but has important effects because of the high commutation speeds. Parasitic inductances tend to maintain their current constant and generate overvoltage during the transistor turn off, resulting in increasing commutation losses.

A parasitic inductance can be associated with each terminal of the MOSFET. They have different effects:

• the gate inductance has little influence (assuming it is lower than some hundreds of nanohenries), because the current gradients on the gate are relatively slow. In some cases, however, the gate inductance and the input capacitance of the transistor can constitute an oscillator. This must be avoided, as it results in very high commutation losses (up to the destruction of the device). On a typical design, parasitic inductances are kept low enough to prevent this phenomenon;
• the drain inductance tends to reduce the drain voltage when the MOSFET turns on, so it reduces turn on losses. However, as it creates an overvoltage during turn-off, it increases turn-off losses;
• the source parasitic inductance has the same behaviour as the drain inductance, plus a feedback effect that makes commutation last longer, thus increasing commutation losses.
  • at the beginning of a fast turn-on, due to the source inductance, the voltage at the source (on the die) will be able to jump up as well as the gate voltage; the internal V_GS voltage will remain low for a longer time, therefore delaying turn-on.
  • at the beginning of a fast turn-off, as current through the source inductance decreases sharply, the resulting voltage across it goes negative (with respect to the lead outside the package) raising the internal V_GS voltage, keeping the MOSFET on, and therefore delaying turn-off.

The gate oxide is very thin (100 nm or less), so it can only sustain a limited voltage. In the datasheets, manufacturers often state a maximum gate to source voltage, around 20 V, and exceeding this limit can result in destruction of the component. Furthermore, a high gate to source voltage reduces significantly the lifetime of the MOSFET, with little to no advantage on R_DSon reduction.

To deal with this issue, a gate driver circuit is often used.

Power MOSFETs have a maximum specified drain to source voltage (when turned off), beyond which breakdown may occur. Exceeding the breakdown voltage causes the device to conduct, potentially damaging it and other circuit elements due to excessive power dissipation.

The drain current must generally stay below a certain specified value (maximum continuous drain current). It can reach higher values for very short durations of time (maximum pulsed drain current, sometimes specified for various pulse durations). The drain current is limited by heating due to resistive losses in internal components such as bond wires, and other phenomena such as electromigration in the metal layer.

The junction temperature (T_J) of the MOSFET must stay under a specified maximum value for the device to function reliably, determined by MOSFET die layout and packaging materials. The packaging often limits the maximum junction temperature, due to the molding compound and (where used) epoxy characteristics.

The maximum operating ambient temperature is determined by the power dissipation and thermal resistance. The junction-to-case thermal resistance is intrinsic to the device and package; the case-to-ambient thermal resistance is largely dependent on the board/mounting layout, heatsinking area and air/fluid flow.

The type of power dissipation, whether continuous or pulsed, affects the maximum operating temperature, due to thermal mass characteristics; in general, the lower the frequency of pulses for a given power dissipation, the higher maximum operating ambient temperature, due to allowing a longer interval for the device to cool down. Models, such as a Foster network, can be used to analyze temperature dynamics from power transients.

The safe operating area defines the combined ranges of drain current and drain to source voltage the power MOSFET is able to handle without damage. It is represented graphically as an area in the plane defined by these two parameters. Both drain current and drain-to-source voltage must stay below their respective maximum values, but their product must also stay below the maximum power dissipation the device is able to handle. Thus, the device cannot be operated at its maximum current and maximum voltage simultaneously.[34]

As described above, the current handling capability of a power MOSFET is determined by its gate channel width. The gate channel width is the third (Z-axis) dimension of the cross-sections pictured.

To minimize cost and size, it is valuable to keep the transistor's die area size as small as possible. Therefore, optimizations have been developed to increase the width of the channel surface area, i.e., increase the "channel density". They mainly consist of creating cellular structures repeated over the whole area of the MOSFET die. Several shapes have been proposed for these cells, the most famous being the hexagonal shape used in International Rectifier's HEXFET devices.

Another way to increase the channel density is to reduce the size of the elementary structure. This allows for more cells in a given surface area, and therefore more channel width. However, as the cell size shrinks, it becomes more difficult to ensure proper contact of every cell. To overcome this, a "strip" structure is often used (see figure). It is less efficient than a cellular structure of equivalent resolution in terms of channel density, but can cope with smaller pitch. Another advantage of the planar stripe structure is that it is less susceptible to failure during avalanche breakdown events in which the parasitic bipolar transistor turns on from sufficient forward bias. In the cellular structure, if the source terminal of any one cell is poorly contacted, then it becomes much more likely that the parasitic bipolar transistor latches on during an avalanche breakdown event. Because of this, MOSFETs utilizing a planar stripe structure can only fail during avalanche breakdown due to extreme thermal stress.[35]

A P-substrate MOSFET (often called PMOS) is a MOSFET with opposite doping types (N instead of P and P instead of N in the cross-section in figure 1). This MOSFET is made using a P-type substrate, with a P⁻ epitaxy. As the channel sits in a N-region, this transistor is turned on by a negative gate to source voltage. This makes it desirable in a buck converter, where one of the terminals of the switch is connected to the high side of the input voltage: with a N-MOSFET, this configuration requires to apply to the gate a voltage equal to ${\displaystyle V_{in}+V_{GS}}$, whereas no voltage over ${\displaystyle V_{in}}$ is required with a P-MOSFET.

The main disadvantage of this type of MOSFET is the poor on-state performance, as it uses holes as charge carriers, which have a much lower mobility than electrons. As resistivity is directly related to mobility, a given PMOS device will have a ${\displaystyle R_{DSon}}$ three times higher than a N-MOSFET with the same dimensions.

The VMOS structure has a V-groove at the gate region and was used for the first commercial devices.[36]

In this power MOSFET structure, also called trench-MOS, the gate electrode is buried in a trench etched in the silicon. This results in a vertical channel. The main interest of the structure is the absence of the JFET effect. The name of the structure comes from the U-shape of the trench.

Especially for voltages beyond 500 V, some manufacturers, including Infineon Technologies with its CoolMOS products, have begun to use a charge compensation principle. With this technology, the resistance of the epitaxial layer, which is the biggest contributor (more than 95%) to the device resistance of high-voltage MOSFETs, can be reduced by a factor of greater than 5.

Seeking to improve the manufacturing efficiency and reliability of super-junction MOSFETs, Renesas Electronics developed a super-junction structure with a deep-trench process technique. This technology entails etching trenches in the low-impurity N-type material to form P-type regions. This process overcomes problems inherent to the multi-level epitaxial growth approach and results in extremely low on-resistance and reduced internal capacitance.

Due to the increased p-n junction area, a super-junction structure has a smaller reverse recovery time but larger reverse recovery current compared to a conventional planar power MOSFET.