Time-to-digital converter

In its simplest implementation, a TDC is simply a high-frequency counter that increments every clock cycle. The current contents of the counter represents the current time. When an event occurs, the counter's value is captured in an output register.

In that approach, the measurement is an integer number of clock cycles, so the measurement is quantized to a clock period. To get finer resolution, a faster clock is needed. The accuracy of the measurement depends upon the stability of the clock frequency.

Typically a TDC uses a crystal oscillator reference frequency for good long term stability. High stability crystal oscillators are usually relative low frequency such as 10 MHz (or 100 ns resolution).[5] To get better resolution, a phase-locked loop frequency multiplier can be used to generate a faster clock. One might, for example, multiply the crystal reference oscillator by 100 to get a clock rate of 1 GHz (1 ns resolution).

High clock rates impose additional design constraints on the counter: if the clock period is short, it is difficult to update the count. Binary counters, for example, need a fast carry architecture because they essentially add one to the previous counter value. A solution is using a hybrid counter architecture. A Johnson counter, for example, is a fast non-binary counter. It can be used to count very quickly the low order count; a more conventional binary counter can be used to accumulate the high order count. The fast counter is sometime called a prescaler.

The speed of counters fabricated in CMOS-technology is limited by the capacitance between the gate and the channel and by the resistance of the channel and the signal traces. The product of both is the cut-off-frequency. Modern chip technology allows multiple metal layers and therefore coils with a large number of windings to be inserted into the chip. This allows designers to peak the device for a specific frequency, which may lie above the cut-off-frequency of the original transistor.

A peaked variant of the Johnson counter is the traveling-wave counter which also achieves sub-cycle resolution. Other methods to achieve sub-cycle resolution include analog-to-digital converters and vernier Johnson counters.

sketch of the coarse counting method in TDCs: showing measurements of T in various relations to the clock pulses

In most situations, the user does not want to just capture an arbitrary time that an event occurs, but wants to measure a time interval, the time between a start event and a stop event.

That can be done by measuring an arbitrary time of both the start and stop events and subtracting. The measurement can be off by two counts.

The subtraction can be avoided if the counter is held at zero until the start event, counts during the interval, and then stops counting after the stop event.

Coarse counters base on a reference clock with signals generated at a stable frequency ${\displaystyle f_{0}}$.[1] When the start signal is detected the counter starts counting clock signals and terminates counting after the stop signal is detected. The time interval ${\displaystyle T}$ between start and stop is then

${\displaystyle T=n\cdot T_{0}}$

with ${\displaystyle n}$, the number of counts and ${\displaystyle T_{0}=1/f_{0}}$, the period of the reference clock.

Since start, stop and clock signal are asynchronous, there is a uniform probability distribution of the start and stop signal-times between two subsequent clock pulses. This detuning of the start and stop signal from the clock pulses is called quantization error.

For a series of measurements on the same constant and asynchronous time interval one measures two different numbers of counted clock pulses ${\displaystyle n_{1}}$ and ${\displaystyle n_{2}}$ (see picture). These occur with probabilities

${\displaystyle p(n_{1})=1-c}$

${\displaystyle q(n_{2})=c}$

with ${\displaystyle c=Frc(T/T_{0})}$ the fractional part of ${\displaystyle T/T_{0}}$. The value for the time interval is then obtained by

${\displaystyle T=(p\cdot n_{1}+q\cdot n_{2})\cdot T_{0}}$

Measuring a time interval using a coarse counter with the averaging method described above is relatively time consuming because of the many repetitions that are needed to determine the probabilities ${\displaystyle p}$ and ${\displaystyle q}$. In comparison to the other methods described later on, a coarse counter has a very limited resolution (1ns in case of a 1 GHz reference clock), but satisfies with its theoretically unlimited measuring range.

When counting is not feasible because the clock rate would be too high, analog methods can be used. Analog methods are often used to measure intervals that are between 10 and 200 ns.[7] These methods often use a capacitor that is charged during the interval being measured.[8][9][10][11] Initially, the capacitor is discharged to zero volts. When the start event occurs, the capacitor is charged with a constant current I₁; the constant current causes the voltage v on the capacitor to increase linearly with time. The rising voltage is called the fast ramp. When the stop event occurs, the charging current is stopped. The voltage on the capacitor v is directly proportional to the time interval T and can be measured with an analog-to-digital converter (ADC). The resolution of such a system is in the range of 1 to 10 ps.[12]

Although a separate ADC can be used, the ADC step is often integrated into the interpolator. A second constant current I₂ is used to discharge the capacitor at a constant but much slower rate (the slow ramp). The slow ramp might be 1/1000 of the fast ramp. This discharge effectively "stretches" the time interval;[13] it will take 1000 times as long for the capacitor to discharge to zero volts. The stretched interval can be measured with a counter. The measurement is similar to a dual-slope analog converter.

The dual-slope conversion can take a long time: a thousand or so clock ticks in the scheme described above. That limits how often a measurement can be made (dead time). Resolution of 1 ps with a 100 MHz (10 ns) clock requires a stretch ratio of 10,000 and implies a conversion time of 150 μs.[13] To decrease the conversion time, the interpolator circuit can be used twice in a residual interpolator technique.[13] The fast ramp is used initially as above to determine the time. The slow ramp is only at 1/100. The slow ramp will cross zero at some time during the clock period. When the ramp crosses zero, the fast ramp is turned on again to measure the crossing time (t_residual). Consequently, the time can be determined to 1 part in 10,000.

Interpolators are often used with a stable system clock. The start event is asynchronous, but the stop event is a following clock.[9][11] For convenience, imagine that the fast ramp rises exactly 1 volt during a 100 ns clock period. Assume the start event occurs at 67.3 ns after a clock pulse; the fast ramp integrator is triggered and starts rising. The asynchronous start event is also routed through a synchronizer that takes at least two clock pulses. By the next clock pulse, the ramp has risen to .327 V. By the second clock pulse, the ramp has risen to 1.327 V and the synchronizer reports the start event has been seen. The fast ramp is stopped and the slow ramp starts. The synchronizer output can be used to capture system time from a counter. After 1327 clocks, the slow ramp returns to its starting point, and interpolator knows that the event occurred 132.7 ns before the synchronizer reported.

The interpolator is actually more involved because there are synchronizer issues and current switching is not instantaneous.[14] Also, the interpolator must calibrate the height of the ramp to a clock period.[15]

The vernier method is more involved.[16] The method involves a triggerable oscillator[17] and a coincidence circuit. At the event, the integer clock count is stored and the oscillator is started. The triggered oscillator has a slightly different frequency than the clock oscillator. For sake of argument, say the triggered oscillator has a period that is 1 ns faster than the clock. If the event happened 67 ns after the last clock, then the triggered oscillator transition will slide by −1 ns after each subsequent clock pulse. The triggered oscillator will be at 66 ns after the next clock, at 65 ns after the second clock, and so forth. A coincidence detector looks for when the triggered oscillator and the clock transition at the same time, and that indicates the fraction time that needs to be added.

The interpolator design is more involved. The triggerable clock must be calibrated to clock. It must also start quickly and cleanly.

The Vernier method is a digital version of the time stretching method. Two only slightly detuned oscillators (with frequencies ${\displaystyle f_{1}}$ and ${\displaystyle f_{2}}$) start their signals with the arrival of the start and the stop signal. As soon as the leading edges of the oscillator signals coincide the measurement ends and the number of periods of the oscillators (${\displaystyle n_{1}}$ and ${\displaystyle n_{2}}$ respectively) lead to the original time interval ${\displaystyle T}$:

${\displaystyle T={\frac {n_{1}-1}{f_{1}}}-{\frac {n_{2}-1}{f_{2}}}}$

Since highly reliable oscillators with stable and accurate frequency are still quite a challenge one also realizes the vernier method via two tapped delay lines using two slightly different cell delay times ${\displaystyle \tau }$. This setting is called differential delay line or vernier delay line.[18]

In the example presented here the first delay line affiliated with the start signal contains cells of D-flip-flops with delay ${\displaystyle \tau _{L}}$ which are initially set to transparent. During the transition of the start signal through one of those cells, the signal is delayed by ${\displaystyle \tau _{L}}$ and the state of the flip-flop is sampled as transparent. The second delay line belonging to the stop signal is composed of a series of non-inverting buffers with delay ${\displaystyle \tau _{B}<\tau _{L}}$. Propagating through its channel the stop signal latches the flip-flops of the start signal's delay line. As soon as the stop signal passes the start signal, the latter is stopped and all leftover flip-flops are sampled opaque. Analogous to the above case of the oscillators the wanted time interval ${\displaystyle T}$ is then

${\displaystyle T=n\cdot (\tau _{1}-\tau _{2})}$

with n the number of cells marked as transparent.

circuit diagram of a tapped delay line

In general a digital delay-line based TDC,[19] also known as tapped delay line, contains a number of cells with well defined delay times ${\displaystyle \tau }$. Propagating through this line the start signal is delayed. The state of the line is sampled at the time of the arrival of the stop signal.

This can be realized for example with a line of D-flip-flop cells with a delay time ${\displaystyle \tau }$. The start signal propagates through this line of transparent flip-flops and is delayed by a certain number of them. The output of each flip-flop is sampled on the fly. The stop signal latches all flip-flops while propagating through its channel undelayed and the start signal cannot propagate further. Now the time interval between start and stop signal is proportional to the number of flip-flops that were sampled as transparent.