Trevor Mudge

Mudge studied at the University of Reading and obtained a Bachelor's degree in Cybernetics, with a minor in Mathematics, in 1969. He then moved to the United States and enrolled in the University of Illinois, where he earned his Master's degree and Doctoral degree in Computer Science in 1973 and 1977, respectively.[1]

Following his Bachelor's degree, Mudge joined the University of Illinois at Urbana-Champaign, and held an appointment as a research assistant in Digital Computer Laboratory in 1970, and in the Coordinated Science Laboratory in 1974. After graduation he joined the University of Michigan in 1977 as Assistant Professor of Electrical Engineering and Computer Science. He was promoted to Associate Professor in 1984, and to Professor of Electrical Engineering and Computer Science in 1990. In 2002 he became the Bredt Family Chair of Computer Science and Electrical Engineering at The University of Michigan.[5]

Mudge has worked extensively on computer architecture, with specific emphasis on computer systems design, computer-aided design, parallel processing, low power computing, and the impact of technology. His research has been characterized by the construction of prototypes as proof of concept.

Mudge and his colleagues developed the concept of runahead.[6] He has shown the effectiveness of point-to-point crossbars for systems with less than a few hundred processors.[7]

Mudge conducted a design study into a fully programmable architecture, SODA, to support software defined radio.[8] An industrial prototype was constructed by the Arm Ltd.[9] He and colleagues developed the first optimal clocking timing algorithms for latch based digital systems: the SMO algorithm.[10][11]

Mudge was one of the first to propose that power be a primary microprocessor design constraint on a par with performance.[12][13] In this connection, he and his colleagues developed “drowsy” caches.[14]

In 2003, Mudge and his colleagues suggested a new approach to DVS, known as Razor, employed in dynamic detection and correction regarding circuit timing errors.[15]

Mudge and his colleagues explored the idea of operating chips at near-threshold voltages to further reduce power consumption.[16] They also built a proof-of-concept prototype 3-dimensional die stacking prototype, and a proof-of-concept prototype 64-core prototype, Centipede. He was an early advocate of 3-dimensional die stacking architecture to save energy.[17]

• 1995 - Fellow, Institute of Electrical and Electronics Engineers, “For contributions to the design and analysis of high-performance processors”
• 1996 - Heaviside Premium. Awarded by the Institution of Electrical Engineer for the best paper of the year: “A comparison of two common pipeline structures” (with M. Golden)
• 2003 - Bredt Family Chair of Engineering, the College of Engineering, University of Michigan[18]
• 2007 - Microprocessor Report Analysts' Choice Award in the Innovation category, “RAZOR—Error-Tolerant Approach Supports Speculative Correctness”
• 2012 - Most Influential Paper Award over the past 10 years from International Conference on Computer-Aided Design’s Ten-Year Retrospective for “Combined dynamic voltage scaling and adaptive body biasing for lower power microprocessors under dynamic workloads” (with S. Martin, K. Flautner, and D. Blaauw)
• 2013 - Life Fellow, IEEE Computer Society
• 2014 - Eckert-Mauchly Award, ACM and IEEE Computer Society, “For pioneering contributions to low-power computer architecture and its interaction with technology”
• 2014 - Int. Conf. Supercomputing 35 most influential paper in the past 25 years for “Improving data cache performance by pre-executing instructions under a cache miss” (with J. Dundas)
• 2017 - Distinguished Achievement Award, University of Illinois Computer Science Department[19]
• 2017 - Fellow, Association for Computing Machinery, “For contributions to power aware computer architecture”
• 2017 – Most Influential Paper Award over the past 15 years for “Drowsy Caches: Simple Techniques for Reducing Leakage Power”, a paper with the most impact over the past 15 years from the ISCA proceedings (with K. Flautner, N. Kim, S. Martin, and D. Blaauw)
• 2018 - Most Impactful Paper—25 years Award, International Conference on High-Performance Computing

• Dundas and T. Mudge. Improving data cache performance by pre-executing instructions under a cache miss. Proc. 1997 ACM Int. Conf. on Supercomputing, July 1997, pp. 68–75.
• Ernst, D., Kim, N. S., Das, S., Pant, S., Rao, R., Pham, T., ...& Mudge, T. (2003, December). Razor: A low-power pipeline based on circuit-level timing speculation. In Proceedings. 36th Annual IEEE/ACM International Symposium on Microarchitecture, 2003. MICRO-36. (pp. 7–18). IEEE.
• Kim, N. S., Austin, T., Baauw, D., Mudge, T., Flautner, K., Hu, J. S., ...& Narayanan, V. (2003). Leakage current: Moore's law meets static power. computer, 36(12), 68-75.
• Flautner, K., Kim, N. S., Martin, S., Blaauw, D., & Mudge, T. (2002). Drowsy caches: Simple techniques for reducing leakage power. ACM SIGARCH Computer architecture news, 30(2), 148-157.
• Dreslinski, R. G., Wieckowski, M., Blaauw, D., Sylvester, D., & Mudge, T. (2010). Near-threshold computing: Reclaiming moore's law through energy efficient integrated circuits. Proceedings of the IEEE, 98(2), 253-266.