Uncore

"Uncore" is a term used by Intel to describe the functions of a microprocessor that are not in the core, but which must be closely connected to the core to achieve high performance.[1] It has been called "system agent" since the release of the Sandy Bridge microarchitecture.[2]

Details

The core contains the components of the processor involved in executing instructions, including the ALU, FPU, L1 and L2 cache. Uncore functions include QPI controllers, L3 cache, snoop agent pipeline, on-die memory controller, on-die PCI Express Root Complex, and Thunderbolt controller.[3] Other bus controllers such as SPI and LPC are part of the chipset.[4]

The Intel uncore design stems from its origin as the northbridge. The design of the Intel uncore reorganizes the functions critical to the core, making them physically closer to the core on-die, thereby reducing their access latency.

Specifically, the microarchitecture of the Intel uncore is broken down into a number of modular units. The main uncore interface to the core is the so-called cache box (CBox), which interfaces with the last level cache (LLC) and is responsible for managing cache coherency. Multiple internal and external QPI links are managed by physical-layer units, referred to as PBox. Connections between the PBox, CBox, and one or more iMCs (MBox) are managed by the system configuration controller (UBox) and a router (RBox).[5]

Removal of serial bus controllers from the Intel uncore further enables increased performance by allowing the uncore clock (UCLK) to run at a base of 2.66 GHz, with overclocking limits in excess of 3.44 GHz.[6] This increased clock rate allows the core to access critical functions (such as the iMC) with significantly less latency, typically reducing core access times to DRAM by 10 ns or more.

References
  1. "Ultrabook, SmartPhone, Laptop, Desktop, Server, & Embedded– Intel". Intel.com. Retrieved 2014-01-21.
  2. Anand Lal Shimpi (September 14, 2010). "Intel's Sandy Bridge Architecture Exposed". AnandTech. Retrieved July 15, 2015.
  3. "Thunderbolt™ Technology for Developers". Intel.com. 2014-01-13. Retrieved 2014-01-21.
  4. "Nehalem: The Unwritten Chapters". AnandTech. Retrieved 2014-01-21.
  5. "Intel(R) Xeon(R) Processor 7500 Series Uncore Programming Guide" (PDF). Retrieved 2014-01-30.
  6. Yus, Carlos (2011-01-27). "HighPerformanceSystems: Intel Sandy Bridge out of specification 4.0, 4.4 and 4.6 GHz. Updated – HighPerformanceSystems". Highperformancesystems.blogspot.com. Retrieved 2014-01-21.
This article is issued from Wikipedia. The text is licensed under Creative Commons - Attribution - Sharealike. Additional terms may apply for the media files.