VLSI Project

In 1975, Carver Mead, Tom Everhart and Ivan Sutherland of Caltech wrote a report for ARPA on the topic of microelectronics. Over the previous few years, Mead had coined the term "Moore's law" to describe Gordon Moore's 1965 prediction for the growth rate of complexity, and in 1974, Robert Dennard of IBM noted that the scale shrinking that formed the basis of Moore's law also affected the performance of the systems. These combined effects implied a massive increase in computing power was about to be unleashed on the industry.[3] The report, published in 1976, suggested that ARPA fund development across a number of fields in order to deal with the complexity that was about to appear due to these "very-large-scale integrated circuits".[4]

Later that year, Sutherland wrote a letter to his brother Bert who was at that time working at Xerox PARC. He suggested a joint effort between PARC and Caltech to begin studying these issues. Bert agreed to form a team, inviting Lynn Conway and Doug Fairbairn to join. Conway had previously worked at IBM on a supercomputer project known as ACS-1. After considering the notes from Mead, Conway realized that the rapid scaling of CMOS being predicted would allow it to surpass the otherwise faster ECL systems used on larger systems as the feature sizes shrank and Dennard's speed predictions kicked in. It also implied that the entire ACS-1 mainframe would one day fit on a single chip.[4] In 1976, Sutherland and Mead wrote an article in Scientific American on the challenges presented by the new complexity.[5]

At the time, microprocessor design was plateauing at the 100,000 transistor level because the tools available to the designers were simply unable to deal with more complex designs. 16-bit and 16/32-bit designs were coming to market, but beyond that seemed too difficult and expensive to contemplate. Mead and Conway felt that there was no theoretical problem impeding progress, simply a number of practical ones, and set about solving these in order to make much more complex designs possible. Simply put, the solution was to simplify everything, inventing new practical rules-of-thumb for designers and applying computers to the problems that were larger.[5] This process was aided by the recent introduction of depletion mode NMOS logic, which greatly simplified the conceptual model of the active elements.[6]

The mid-1970s were a period of rapid change as new processes were being introduced at different companies at a rapid pace. Each new process led to a set of design rules that often ran to 40 pages. These would include details like "do not place to parallel lines on the metallization layer (MET) that are closer than 2 micrometers apart". Dozens of such rules were developed for each layer to squeeze out maximum performance. In early 1977, Conway began developing a new set of completely generic rules. These would not offer the highest performance possible for any given system, but her concept was that it would so greatly reduce design time that it could be adapted to a new underling fabrication technology with little or no changes, and such a move would offer many times the performance benefit that using every published trick of the existing rules would.[6]

Starting with three colored whiteboard pens representing each of the types of layers, MET, POLY, DIFF, Conway developed a set of design rules that worked on every current process. Further development led to the realization that all of the dimensions could be expressed as multiples of some fundamental minimum feature size possible using that process, which became known as λ (the Greek letter lambda). λ was set to be one half of the minimum width of a line of POLY or DIFF, and the rules expressed in those terms; "a line has to be two λ wide", "two lines on the same layer must be at least three λ apart", "lines on different layers must be one λ apart" and so forth. The end result was a short set of design rules that applied at any scale. Conway later noted "I vividly recall seeing Mead's jaw drop that spring morning in 1977 as I presented my strategy for λ-based rules on my whiteboard at PARC."[7]

One of the primary efforts under VLSI was the creation of the hardware and software needed to automate the design process, which at that point was still largely manual. For a design containing hundreds of thousands of transistors, there was simply no machine short of a supercomputer that had the memory and performance needed to work on the design as a whole.

To address this problem, and thereby allow "average" companies to use automated tools, VLSI funded the Geometry Engine and Pixel-Planes projects at Stanford University and University of North Carolina at Chapel Hill (respectively) to create suitable graphics hardware at the desktop level. The former evolved into an effort to design a networked CAD workstation, known as the Stanford University Network. This is better known today under its acronym, "SUN", as in Sun Microsystems, which commercialized the design.

To provide a common software platform to run these new tools, VLSI also funded a Berkeley project to provide a standardized Unix implementation, known today as the Berkeley Software Distribution (BSD). Almost all early workstations used BSD, including designs that evolved into Sun, SGI, Apollo Computer, and others. BSD later spawned several descendants, OpenBSD, FreeBSD, NetBSD, and DragonFlyBSD.

CAD software was an important part of the VLSI effort. This led to major improvements in CAD technology for layout, design rule checking, and simulation. The tools developed in this program were used extensively in both academic research programs and in industry. The ideas were developed in commercial implementations by companies such as VLSI Technology, Cadnetix, and Synopsis.

With these tools in hand, other VLSI funded projects were able to make huge strides in design complexity, sparking off the RISC revolution. The two major VLSI-related projects were Berkeley RISC and Stanford MIPS, both of which relied heavily on the tools developed in previous VLSI projects. To allow design teams to produce test examples, the project also funded the building of their own fabrication facility, MOSIS (Metal Oxide Semiconductor Implementation Service), which received plans electronically. MOSIS remains in operation today.

Another important part of the MOSIS fabrication process was the development of the multichip wafer, which allowed a single wafer of silicon to be used to produce several chip designs at the same time. Previously a wafer would normally be used to produce a single design, which meant that there was a definite minimum production run one could consider starting up. In contrast, the multichip wafer a small batch of a chip design could be produced in the middle of a larger run, dramatically lowering the startup cost and prototyping stage.

• Conway, Lynn (Fall 2012). "Reminiscences of the VLSI Revolution" (PDF). IEEE Solid-State Circuits Magazine. 4 (44): 8–31. doi:10.1109/MSSC.2012.2215752. S2CID 9286356.