XAP processor

The first XAP processor was XAP1, designed in 1994 and used for a number of wireless and sensor ASIC projects at Cambridge Consultants. It was a very small, 3,000-gate, Harvard architecture, 16-bit processor with a 16-bit data bus and an 18-bit instruction bus intended for running programs stored in on-chip read-only memory or ROM. Data and instructions were each addressed by separate 16-bit address bus.

A more powerful XAP2 was developed and used from 1999. It also had a Harvard architecture and 16-bit data, and it adopted a more conventional 16-bit instruction width suitable for program storage in Flash or other off-chip memories. Large programs were accommodated by a 24-bit address bus for instructions and there was a 16-bit address bus for data. XAP2 was a 12,000-gate processor with support for interrupts and a software tool chain including a C compiler and the XAPASM assembler for its assembly language. XAP2 was also used in Cambridge Consultants' ASIC designs, and it was also provided to other semiconductor companies as a semiconductor intellectual property core, or IP core.

XAP2 was adopted by three fabless semiconductor companies that emerged from Cambridge Consultants: CSR plc (Cambridge Silicon Radio) is the main provider of Bluetooth chips for mobile phones and headsets; Ember Corporation is a leading supplier of Zigbee chips; and Cyan Technology supplies XAP2-powered microcontrollers. As a consequence and combined with other licensees and Cambridge Consultants’ ASIC projects, there are now over one billion (1,000 million) XAP processors in use worldwide.

XAP3 was an experimental 32-bit processor designed at Cambridge Consultants in 2003. It was optimised for low cost, low energy ASIC implementations using modern CMOS semiconductor process technologies. The instruction set was optimised for GNU GCC to achieve high code density. The XAP3 was the first of Cambridge Consultants’ processors to use a Von Neumann architecture with a logically shared address space for Program and Data. The physical program memory could be Flash or one-time programmable EPROM or SRAM. ASIC design was simplified by using a single memory where there was no need to pre-determine the split between Program (instructions) and Data at design time. The XAP3's instruction set with the GCC compiler produced very high code density. This reduced the size of the program memory, which reduced the chip unit cost and reduced the energy consumption.

In 2005, further project requirements saw a new 16-bit processor, the XAP4, designed to supersede the XAP2 taking into account the experience gained on XAP3 and the evolving requirements of ASIC designs. XAP4 is a very small, 12,000-gate, Von Neumann bus, 16-bit processor core capable of addressing a total of 64 Kbytes of memory for programs, data and peripherals. It offers high code density combined with good performance in the region of 50 Dhrystone MIPS when clocked at 80 MHz XAP4 was designed for use in modern ASIC or microcontroller applications capable of processing real-world data captured by an analog-to-digital converter (ADC) or similar sources. The processor's 16-bit integer word supports the precision of most ADCs without carrying the overhead of a 32-bit processor. XAP4 also offers a migration path from 8-bit processors, such as 8051, in applications that need increased performance and program size, but cannot justify the cost and overhead of a 32-bit processor. The XAP4 registers (all 16-bit) are; 8 General Purpose, Program Counter, Vector Pointer, FLAGS, INFO, BRKE, 2 Breakpoint. The XAP4 instructions are 16 and 32-bit. The XAP4 compile chain is based on GNU GCC and Binutils.

Development of an extended version of this architecture commenced in 2006 and resulted in the XAP5, which was announced in July 2008. XAP5 is a 16-bit processor with a 24-bit address bus making it capable of running programs from memory up to 16 MBytes. XAP4 and XAP5 are both implemented with a two-stage instruction pipeline, which maximises their performance when clocked at low frequencies. This is tailored to the requirements of small, low-energy ASICs as it minimises processor hardware size (the XAP5 core uses 18,000-gates), and it fits designs that are clocked relatively slowly to reduce an ASIC's dynamic power consumption and run programs direct from Flash or OTP memory that has a slow access time. Typical clock speeds for XAP5 are in the range of 16 to 100 MHz on a 0.13 process. XAP5 has particular design features making it suitable for executing programs from Flash including a Vector Pointer and an Address Translation Window, which combine to allow in-place execution of programs and relocation of programs regardless of where they are stored in physical memory. The XAP4 registers (16 and 24-bit) are; 8 General Purpose, Program Counter, Vector Pointer, FLAGS, INFO, BRKE, 4 Breakpoint. The XAP5 instructions are 16, 32 and 48-bit. The XAP5 compile chain is based on GNU GCC and Binutils.

XAP6 is a 32-bit processor and was launched in 2013. It has the same type of load-store architecture as the XAP4 and XAP5, but has 32-bit registers and 32-bit buses for Data and Address. The XAP6a implementation has a three-stage instruction pipeline. Like all the XAP processors, the XAP6 has been optimised for low-cost, low-energy and easy verification. XAP6 is tailored for small low-energy ASICs and minimises processor hardware size (the XAP6 core uses 30,000-gates). The XAP6 registers (all 32-bit) are; 8 General Purpose, Program Counter, Vector Pointer, Global Pointer, FLAGS, INFO, BRKE, 4 Breakpoint. The XAP6 instructions are 16, 32 and 48-bit. The XAP6 compile chain is based on GNU GCC and Binutils.