Extensible Host Controller Interface

The OHCI and UHCI controllers support only USB 1 speed devices (1.5 Mbit/s and 12 Mbit/s), and the EHCI only supports USB 2 devices (480 Mbit/s).

The xHCI architecture was designed to support all USB speeds, including SuperSpeed (5 Gbit/s) and future speeds, under a single driver stack.

When USB was originally developed in 1995, it was targeted at desktop platforms to stem the proliferation of connectors that were appearing on PCs, e.g. PS/2, serial port, parallel port, game port, etc., and host power consumption was not an important consideration at the time. Since then, mobile platforms have become the platform of choice, and their batteries have made power consumption a key consideration. The architectures of the legacy USB host controllers (OHCI, UHCI, and EHCI) were very similar in that the "schedule" for the transactions to be performed on the USB were built by software in host memory, and the host controller hardware would continuously read the schedules to determine what transactions needed to be driven on the USB, and when, even if no data was moved. Additionally, in the case of reads from the device, the device was polled each schedule interval, even if there was no data to read.

• The xHCI eliminates host memory based USB transaction schedules, enabling zero host memory activity when there is no USB data movement.
• The xHCI reduces the need for periodic device polling by allowing a USB 3.0 or later device to notify the host controller when it has data available to read, and moves the management of polling USB 2.0 and 1.1 devices that use interrupt transactions from the CPU-driven USB driver to the USB host controller. EHCI, OHCI, and UHCI host controllers would automatically handle polling for the CPU if there are no changes that need to be made and if no device has any interrupts to send but they all rely on the CPU to set the schedule up for the controllers.[1][2][3] If any USB device using interrupt transactions does have data to send, then an xHCI host controller will send an interrupt to notify the CPU that there is a USB interrupt transaction that needs handling. Since the CPU no longer has to manage the polling of the USB bus, it can spend more time in low power states.
• The xHCI does not require that implementations provide support for all advanced USB 2 and 3 power management features, including USB 2 LPM, USB 3 U1 and U2 states, HERD, LTM, Function Wake, etc.; but these features are required to realize all of the advantages of xHCI.

Legacy USB host-controller architectures exhibit some serious shortcomings when applied to virtualized environments. Legacy USB host-controller interfaces define a relatively simple hardware data-pump; where critical state related to overall bus-management (bandwidth allocation, address assignment, etc.) resides in the software of the host-controller driver (HCD). Trying to apply the standard hardware IO virtualization technique - replicating I/O interface registers - to the legacy USB host controller interface is problematic because critical state that must be managed across virtual machines (VMs) is not available to hardware. The xHCI architecture moves the control of this critical state into hardware, enabling USB resource management across VMs. The xHCI virtualization features also provide for:

• direct-Assignment of individual USB devices (irrespective of their location in the bus topology) to any VM
• minimizing run-time inter-VM communications
• support for native USB device-sharing
• support of PCIe SR-IOV (single root I/O virtualization)

The EHCI utilizes OHCI or UHCI controllers as "companion controllers", where USB 2 devices are managed through the EHCI stack, and the port logic of the EHCI allows a low-speed or full-speed USB device to be routed to a port of a "companion" UHCI or OHCI controller, where the low-speed or full-speed USB devices are managed through the respective UHCI or OHCI stack. For example, a USB 2 PCIe host controller card that presents 4 USB "Standard A" connectors typically presents one 4-port EHCI and two 2-port OHCI controllers to system software. When a high-speed USB device is attached to any of the 4 connectors, the device is managed through one of the 4 root hub ports of the EHCI controller. If a low-speed or full-speed USB device is attached to connectors 1 or 2, it will be routed to the root hub ports of one of the OHCI controllers for management, and low-speed and full-speed USB devices attached to connectors 3 or 4 will be routed to the root hub ports of the other OHCI controller. The EHCI dependence on separate host controllers for high-speed USB devices and the group of low-speed and full-speed USB devices results in complex interactions and dependencies between the EHCI and OHCI/UHCI drivers.

• The xHCI architecture eliminates the need for companion controllers and their separate driver stacks.
• The incorporation of the schedule, bandwidth management, and USB device address assignment functions, that were previously performed by the driver in to the xHCI hardware enable a simpler, leaner, lower latency software stack for the xHCI.

Support for Streams was added to the USB 3.0 SuperSpeed specification, primarily to enable high performance storage operations over USB. Classically there has been a 1:1 relationship between a USB endpoint and a buffer in system memory, and the host controller solely responsible for directing all data transfers. Streams changed this paradigm by providing a 1-to-many "endpoint to buffer" association, and allowing the device to direct the host controller as to which buffer to move. The USB data transfers associated with a USB Stream endpoint are scheduled by the xHCI the same as any other bulk endpoint is, however the data buffer associated with a transfer is determined by the device.

• The xHCI USB Stream support allows up to 64K buffers to be associated with a single endpoint.
• The xHCI Streams protocol support allows a USB device to select which buffer that the xHCI will transfer when the endpoint is scheduled.

The xHCI architecture was designed to be highly scalable, capable of supporting 1 to 255 USB devices and 1 to 255 root hub ports. Since each USB device is allowed to define up to 31 endpoints, an xHCI that supported 255 devices would have to support 7,906 separate total endpoints. Classically, each memory buffer associated with an endpoint is described by a queue of physical memory blocks, where the queue requires a head pointer, tail pointer, length and other registers to define its state. There are many ways to define queue state, however if one were to assume 32 bytes of register space for each queue, then almost a 256KB of register space would be required to support 7,906 queues. Typically only a small number of USB devices are attached to a system at one time, and on the average a USB device supports 3-4 endpoints, of which only a subset of the endpoints are active at the same time. The xHCI maintains queue state in system memory as Endpoint Context data structures. The contexts are designed so that they can be cached by the xHCI, and "paged" in and out as a function of endpoint activity. Thus a vendor can scale their internal xHCI Endpoint Context cache space and resources to match the practical usage models expected for their products, rather than the architectural limits that they support. Ideally the internal cache space is selected so that under normal usage conditions, there is no context paging by the xHCI. Also USB endpoint activity tends to be bursty. That is, at any point in time a large number of endpoints may be ready to move data, however only a subset are actively moving data. For instance, the interrupt IN endpoint of a mouse may not transfer data for hours if the user is away from their desk. xHCI vendor specific algorithms could detect this condition and make that endpoint a candidate for paging out if other endpoints become busy.

• The xHCI architecture allows large maximum values for the number of USB devices, ports, interrupt vectors, etc. supported, however an implementation only needs to define the number necessary to meet its marketing requirements. For instance, a vendor could choose to limit the number of USB devices that it supported for a tablet xHCI implementation to 16 devices.
• A vendor can further take advantage of xHCI architectural features to scale its internal resources to match its target usage models. For instance, if through usability testing a vendor determines that 95% of tablet users will never connect more than 4 USB devices, and each USB device typically defines 4 endpoints (or less), then internal caching for 16 Endpoint Contexts will ensure that under normal conditions there will be no system memory activity due to Endpoint Context paging.

The xHCI specification uses "errata" files to define updates and clarifications to a specific release. The changes in the errata files are accumulated in each release. Refer to the associated errata files for the details of specific changes. Most changes defined in the xHCI errata files are clarifications, grammatical or spelling corrections, additional cross-references, etc., which do not affect a driver implementation. Changes that are determined to be architectural utilize a Capability flag to determine whether a particular feature is supported by an xHCI implementation, and an Enable flag to turn on the feature.

The xHCI specification evolved through several versions before its official release in 2010:

• xHCI 0.9: Released in August 2008.
• USB 0.95: Released in December 2008.
• USB 0.96: Released in August 2009.
• USB 0.96a: 1.0 Release Candidate, Released in April 2010. First shipping devices based on this version.

• xHCI 1.0: First public release, May 21, 2010.
  Specified USB data rates of 1.5 Mbit/s (Low-speed), 12 Mbit/s (Full-speed), 480 Mbit/s (High-speed) and 5 Gbit/s (SuperSpeed).
• xHCI 1.0, errata files 1-4: Released on January 17, 2011.
  Incorporated initial review feedback from larger 1.0 public audience, Save-Restore clarifications, and Hardware LPM support.
• xHCI 1.0, errata files 1-6: Released on March 18, 2011.
  Clarifications.
• xHCI 1.0, errata files 1-7: Released on June 13, 2011.
  Clarifications.

• xHCI 1.1: Released on December 21, 2013. Specified USB 3.1 data rate of 10 Gbit/s (SuperSpeed+). This incorporates xHCI 1.0 errata files 1-21. Allows controller to require a larger number of scratchpad buffers (up to 1023) in HCSPARAMS2 capability register.

• xHCI 1.2: Dated May 2019. Specified USB 3.2 data rates of 10 Gbit/s (SuperSpeedPlus Gen1x2) and 20 Gbit/s (SuperSpeedPlus Gen2x2).[5]