Zero register

A zero register is a processor register that always returns the value zero. It is found primarily in high-performance instruction set architectures, notably the CDC 6600, System/360 and MIPS architecture, among others.

Zero appears as a constant in many instructions, notably "branch if zero", and optimizing these instructions can have a significant positive benefit on performance. Some architectures accomplish this with dedicated opcodes, specialized variations of their basic instructions. Implementing these requires additional logic in the instruction decoder. The zero register can accomplish the same effect without requiring new opcodes, although at the cost of dedicating a register to this feature, which can be expensive in circuitry terms.

Most modern architectures, such as x86 and ARM, omit the zero register; however a notable exception would be the RISC-V architecture, which includes one with the register name "x0" and the ABI name "zero." The reason for this inclusion is stated as "Dedicating a register to zero is surprisingly a large factor in simplifying the RISC-V ISA."[1]

References

Patterson, David. The RISC-V Reader: An Open Architecture Atlas (Beta Ed., 0.0.1 ed.). p. 18.

Mashey, John (8 August 1998). "Top 10 Mistakes in Computer Architecture".
"RISC-V Spec" (PDF).

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[1] Patterson, David. The RISC-V Reader: An Open Architecture Atlas (Beta Ed., 0.0.1 ed.). p. 18.