Altera

Cyclone III FPGA

FPGA Developer-board with Altera Cyclone V SE FPGA

The Stratix series FPGAs were the company's largest, highest bandwidth devices, with up to 1.1 million logic elements, integrated transceivers at up to 28 Gbit/s, up to 1.6 Tbit/s of serial switching capability, up to 1,840 GMACs of signal-processing performance, and up to 7 x72 DDR3 memory interfaces at 800 MHz.[6]

In September 2000, the company acquired Northwest Logic to expand its design services for delivery of complete system-on-chip solutions.[7]

In May 2013, Altera made available SDK for OpenCL, enabling software programmers to access the high-performance capabilities of programmable logic devices.[8]

Beginning in December 2012, the company produced system on a chip FPGA devices using a fully depleted silicon on insulator (FDSOI) chip manufacturing process. These devices integrated FPGAs with full hard processor systems based around ARM architecture onto a single device.[9][10]

In May 2013, Altera acquired embedded power chipmaker Enpirion for approximately $140 million in cash, providing Altera with power system on a chip DC-DC converters that enabled greater power densities and lower noise performance compared with their discrete equivalent. Unlike converters made from discrete components, Enpirion DC-DC converters were simulated, characterized, validated and production qualified at delivery.[11]

Altera offered a publicly available ASIC design flow based on HardCopy ASICs, which transitioned an FPGA design, once finalized, to a form which is not alterable. This design flow reduced design security risks as well as costs for higher volume production. Design engineers could prototype their designs in Stratix series FPGAs, and then migrate these designs to HardCopy ASICs when they were ready for volume production.

The unique design flow made hardware/software co-design and co-verification possible. The flow was benchmarked to deliver systems to market 9 to 12 months faster, on average, than with standard-cell solutions. Design engineers were able to employ a single RTL, set of intellectual property (IP) cores, and Quartus II design software for both FPGA and ASIC implementations. Altera's HardCopy Design Center managed test insertion.

In 2007, Altera’s Nios II FPGA soft processor core became available for standard cell ASIC designs.[12]

Altera and its partners offered an array of semiconductor intellectual property cores that served as building blocks that design engineers can drop into their system designs to perform specific functions. IP cores eliminate some of the time-consuming tasks of creating every block in a design from scratch. In 2000, Altera acquired Designpro, a provider of IP cores.[13]

Altera offered soft processor cores on the Nios II embedded processor, the Freescale ColdFire v1 core (free for Cyclone III FPGA), and the ARM Cortex-M1 processor as well as a hard IP processor core on the ARM Cortex-A9 processor.

All of Altera's devices were supported by a common design environment, Quartus II design software. Quartus II software was available in a subscription-based edition and a free Web-based edition. It included tools to foster productivity.

In May 2008, Altera introduced the first 40-nm programmable logic devices: the Stratix IV FPGAs and HardCopy IV ASICs.[14] Both devices were available with integrated transceiver options.

In February 2009, the company introduced Stratix IV GT FPGAs, which had 11.3 Gbit/s transceivers for 40G/100G applications,[15] and Arria II GX FPGAs, which had 3.75 Gbit/s transceivers for power- and cost-sensitive applications.

Altera's devices were manufactured using techniques such as 193-nm immersion lithography and technologies such as extreme low-k dielectrics and strained silicon.

In April 2010, Altera introduced the FPGA industry's second 28-nm device, the Stratix V FPGA (to Xilinx's Kintex-7 FPGA), available with transceivers at speeds up to 28 Gbit/s. This device family has more than 1 million logic elements, up to 53 Mb of embedded memory, up to 7 x72 DDR3 DIMMs at 800 MHz, 1.6 Gbit/s LVDS performance, and up to 3,680 variable-precision DSP blocks.

In August 2011, Altera began shipping 28-nm Stratix V GT devices featuring 28-gigabits-per-second transceivers.[16][17]

Embedded HardCopy blocked harden standard or logic-intensive applications, increasing integration and delivering twice the density without a cost or power penalty. Altera developed a user-friendly method for partial reconfiguration, so core functionality can be changed easily and on the fly. There is a path to HardCopy V ASICs, when designs are ready for volume production. Altera’s 28 nm FPGAs aimed to reduce power requirements to 200 mW per channel.[16] In 2004, the company began collaborating with Synopsys on HardCopy Structured ASICs.[18]

In December 2012, the company announced the shipment of its first 28 nm Cyclone V SoC devices, which had a dual-core ARM architecture Cortex-A9 processor system with FPGA logic on a single chip.[19] These SoCs were targeted for wireless communications, industrial, video surveillance, automotive and medical equipment markets. With these SoCs devices, users were able to create custom field-programmable SoC variants for power, board space, performance and cost optimization.[20]

In February 2013, Altera announced an agreement with Intel to use Intel’s foundry services to produce its 14-nm node for the future manufacturing of its FPGAs, based on Intel’s 14 nm tri-gate transistor technology, in place of Altera’s ongoing agreement with TSMC.[21]

In October 2016, nearly one year after Intel's integration with Altera, STRATIX 10 was announced, which is based on Intel's 14 nm Tri-Gate process.[22]