VHDL

In 1983, VHDL was originally developed at the behest of the U.S. Department of Defense in order to document the behavior of the ASICs that supplier companies were including in equipment. The standard MIL-STD-454N[2] in Requirement 64 in section 4.5.1 "ASIC documentation in VHDL" explicitly requires documentation of "Microelectronic Devices" in VHDL.

The idea of being able to simulate the ASICs from the information in this documentation was so obviously attractive that logic simulators were developed that could read the VHDL files. The next step was the development of logic synthesis tools that read the VHDL and output a definition of the physical implementation of the circuit.

Due to the Department of Defense requiring as much of the syntax as possible to be based on Ada, in order to avoid re-inventing concepts that had already been thoroughly tested in the development of Ada, VHDL borrows heavily from the Ada programming language in both concept and syntax.

The initial version of VHDL, designed to IEEE standard IEEE 1076-1987,[3] included a wide range of data types, including numerical (integer and real), logical (bit and boolean), character and time, plus arrays of bit called bit_vector and of character called string.

A problem not solved by this edition, however, was "multi-valued logic", where a signal's drive strength (none, weak or strong) and unknown values are also considered. This required IEEE standard 1164, which defined the 9-value logic types: scalar std_logic and its vector version std_logic_vector. Being a resolved subtype of its std_Ulogic parent type, std_logic-typed signals allow multiple driving for modeling bus structures, whereby the connected resolution function handles conflicting assignments adequately.

The updated IEEE 1076, in 1993, made the syntax more consistent, allowed more flexibility in naming, extended the character type to allow ISO-8859-1 printable characters, added the xnor operator, etc.

Minor changes in the standard (2000 and 2002) added the idea of protected types (similar to the concept of class in C++) and removed some restrictions from port mapping rules.

In addition to IEEE standard 1164, several child standards were introduced to extend functionality of the language. IEEE standard 1076.2 added better handling of real and complex data types. IEEE standard 1076.3 introduced signed and unsigned types to facilitate arithmetical operations on vectors. IEEE standard 1076.1 (known as VHDL-AMS) provided analog and mixed-signal circuit design extensions.

Some other standards support wider use of VHDL, notably VITAL (VHDL Initiative Towards ASIC Libraries) and microwave circuit design extensions.

In June 2006, the VHDL Technical Committee of Accellera (delegated by IEEE to work on the next update of the standard) approved so-called Draft 3.0 of VHDL-2006. While maintaining full compatibility with older versions, this proposed standard provides numerous extensions that make writing and managing VHDL code easier. Key changes include incorporation of child standards (1164, 1076.2, 1076.3) into the main 1076 standard, an extended set of operators, more flexible syntax of case and generate statements, incorporation of VHPI (VHDL Procedural Interface) (interface to C/C++ languages) and a subset of PSL (Property Specification Language). These changes should improve quality of synthesizable VHDL code, make testbenches more flexible, and allow wider use of VHDL for system-level descriptions.

In February 2008, Accellera approved VHDL 4.0, also informally known as VHDL 2008, which addressed more than 90 issues discovered during the trial period for version 3.0 and includes enhanced generic types. In 2008, Accellera released VHDL 4.0 to the IEEE for balloting for inclusion in IEEE 1076-2008. The VHDL standard IEEE 1076-2008[4] was published in January 2009.

VHDL is generally used to write text models that describe a logic circuit. Such a model is processed by a synthesis program, only if it is part of the logic design. A simulation program is used to test the logic design using simulation models to represent the logic circuits that interface to the design. This collection of simulation models is commonly called a testbench.

A VHDL simulator is typically an event-driven simulator.[12] This means that each transaction is added to an event queue for a specific scheduled time. E.g. if a signal assignment should occur after 1 nanosecond, the event is added to the queue for time +1ns. Zero delay is also allowed, but still needs to be scheduled: for these cases delta delay is used, which represent an infinitely small time step. The simulation alters between two modes: statement execution, where triggered statements are evaluated, and event processing, where events in the queue are processed.

VHDL has constructs to handle the parallelism inherent in hardware designs, but these constructs (processes) differ in syntax from the parallel constructs in Ada (tasks). Like Ada, VHDL is strongly typed and is not case sensitive. In order to directly represent operations which are common in hardware, there are many features of VHDL which are not found in Ada, such as an extended set of Boolean operators including nand and nor.

VHDL has file input and output capabilities, and can be used as a general-purpose language for text processing, but files are more commonly used by a simulation testbench for stimulus or verification data. There are some VHDL compilers which build executable binaries. In this case, it might be possible to use VHDL to write a testbench to verify the functionality of the design using files on the host computer to define stimuli, to interact with the user, and to compare results with those expected. However, most designers leave this job to the simulator.

It is relatively easy for an inexperienced developer to produce code that simulates successfully but that cannot be synthesized into a real device, or is too large to be practical. One particular pitfall is the accidental production of transparent latches rather than D-type flip-flops as storage elements.[13]

One can design hardware in a VHDL IDE (for FPGA implementation such as Xilinx ISE, Altera Quartus, Synopsys Synplify or Mentor Graphics HDL Designer) to produce the RTL schematic of the desired circuit. After that, the generated schematic can be verified using simulation software which shows the waveforms of inputs and outputs of the circuit after generating the appropriate testbench. To generate an appropriate testbench for a particular circuit or VHDL code, the inputs have to be defined correctly. For example, for clock input, a loop process or an iterative statement is required.[14]

A final point is that when a VHDL model is translated into the "gates and wires" that are mapped onto a programmable logic device such as a CPLD or FPGA, then it is the actual hardware being configured, rather than the VHDL code being "executed" as if on some form of a processor chip.

The key advantage of VHDL, when used for systems design, is that it allows the behavior of the required system to be described (modeled) and verified (simulated) before synthesis tools translate the design into real hardware (gates and wires).

Another benefit is that VHDL allows the description of a concurrent system. VHDL is a dataflow language in which every statement is considered for execution simultaneously, unlike procedural computing languages such as BASIC, C, and assembly code, where a sequence of statements is run sequentially one instruction at a time.

A VHDL project is multipurpose. Being created once, a calculation block can be used in many other projects. However, many formational and functional block parameters can be tuned (capacity parameters, memory size, element base, block composition and interconnection structure).

A VHDL project is portable. Being created for one element base, a computing device project can be ported on another element base, for example VLSI with various technologies.

A big advantage of VHDL compared to original Verilog is that VHDL has a full type system. Designers can use the type system to write much more structured code (especially by declaring record types).[15]

In VHDL, a design consists at a minimum of an entity which describes the interface and an architecture which contains the actual implementation. In addition, most designs import library modules. Some designs also contain multiple architectures and configurations.

A simple AND gate in VHDL would look something like

-- (this is a VHDL comment)
/*
    this is a block comment (VHDL-2008)
*/
-- import std_logic from the IEEE library
library IEEE;
use IEEE.std_logic_1164.all;

-- this is the entity
entity ANDGATE is
  port ( 
    I1 : in std_logic;
    I2 : in std_logic;
    O  : out std_logic);
end entity ANDGATE;

-- this is the architecture
architecture RTL of ANDGATE is
begin
  O <= I1 and I2;
end architecture RTL;

(Notice that RTL stands for Register transfer level design.) While the example above may seem verbose to HDL beginners, many parts are either optional or need to be written only once. Generally simple functions like this are part of a larger behavioral module, instead of having a separate module for something so simple. In addition, use of elements such as the std_logic type might at first seem to be an overkill. One could easily use the built-in bit type and avoid the library import in the beginning. However, using a form of many-valued logic, specifically 9-valued logic (U,X,0,1,Z,W,H,L,-), instead of simple bits (0,1) offers a very powerful simulation and debugging tool to the designer which currently does not exist in any other HDL.

In the examples that follow, you will see that VHDL code can be written in a very compact form. However, more experienced designers usually avoid these compact forms and use a more verbose coding style for the sake of readability and maintainability.

X <= A when S = '1' else B;

library IEEE;
use IEEE.std_logic_1164.all;
entity mux4 is
port(
  a1      : in  std_logic_vector(2 downto 0);
  a2      : in  std_logic_vector(2 downto 0);
  a3      : in  std_logic_vector(2 downto 0);
  a4      : in  std_logic_vector(2 downto 0);
  sel     : in  std_logic_vector(1 downto 0);
  b       : out std_logic_vector(2 downto 0));
end mux4;
architecture rtl of mux4 is
  -- declarative part: empty
begin
p_mux : process(a1,a2,a3,a4,sel)
begin
  case sel is
    when "00" => b <= a1 ;
    when "01" => b <= a2 ;
    when "10" => b <= a3 ;
    when others => b <= a4 ;
  end case;
end process p_mux;
end rtl;

-- latch template 1:
Q <= D when Enable = '1' else Q;

-- latch template 2:
process(all)
begin
    Q <= D when(Enable);

end process;
use IEEE.STD_LOGIC_1164.ALL;

entity dflip is

end dflip;

architecture structural of dflip is

    component AND2
        port (in1, in2:in std_logic; out1: out std_logic);
    end component;

    component OR2
        port (in1, in2:in std_logic; out1: out std_logic);
    end component;

    component NOT1
        port (in1: in std_logic; out1: out std_logic);
    end component;

    signal D, E, E_NOT, Q, OUT_AND1, OUT_AND2: std_logic;

begin   
    U0: NOT1    port map (E, E_NOT);
    U1: AND2    port map (E, D, OUT_AND1);
    U2: AND2    port map (E_NOT, Q, OUT_AND2);
    U3: OR2     port map (OUT_AND1, OUT_AND2, Q);
end structural;


entity NOT1 is
    port (in1: in std_logic; out1: out std_logic);
end NOT1;

architecture behavioral_not of NOT1 is
begin
    out1 <= not in1;
end behavioral_not;


entity AND2 is
    port(in1, in2: in std_logic; out1: out std_logic);
end AND2;

architecture behavioral_and2 of AND2 is
begin

    out1 <= in1 and in2;

end behavioral_and2;


entity OR2 is
    port (in1, in2: in std_logic; out1: out std_logic);
end OR2;

architecture behavioral_or of OR2 is
begin
    out1 <= in1 or in2;
end behavioral_or;

DFF : process(all) is
begin
  if RST then
    Q <= '0';
  elsif rising_edge(CLK) then
    Q <= D;
  end if;
end process DFF;

DFF : process(RST, CLK) is
begin
  if RST then
    Q <= '0';
  elsif CLK'event and CLK = '1' then
    Q <= D;
  end if;
end process DFF;

DFF : Q <= '0' when RST = '1' else D when rising_edge(clk);

DFF : process(all) is 
begin
  if rising_edge(CLK) then
    Q  <= D;
    Q2 <= Q1;
  end if;
  if RST then
    Q <= '0';
  end if;
end process DFF;

  port(
     Q : out std_logic;    
     Clk :in std_logic;  
  sync_reset: in std_logic;  
     D :in  std_logic    
  );

process(Clk)
begin 
   if(rising_edge(Clk)) then
  if(sync_reset='1') then 
   Q <= '0';
  else 
   Q <= D; 
  end if;
   end if;       
end process;  

library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;    -- for the unsigned type

entity COUNTER is
  generic (
    WIDTH : in natural := 32);
  port (
    RST   : in std_logic;
    CLK   : in std_logic;
    LOAD  : in std_logic;
    DATA  : in std_logic_vector(WIDTH-1 downto 0);
    Q     : out std_logic_vector(WIDTH-1 downto 0));
end entity COUNTER;

architecture RTL of COUNTER is

begin
  process(all) is
  begin
    if RST then
      Q <= (others => '0');
    elsif rising_edge(CLK) then
      if LOAD then
        Q <= DATA;
      else
        Q <= std_logic_vector(unsigned(Q) + 1); --Addition is unsigned, converted back to std_logic_vector
      end if;
    end if;
  end process;

end architecture RTL;

process
begin
  CLK <= '1'; wait for 10 NS;
  CLK <= '0'; wait for 10 NS;
end process;

process
begin
  wait until START = '1'; -- wait until START is high
  
  for i in 1 to 10 loop -- then wait for a few clock periods...
    wait until rising_edge(CLK);
  end loop;

  for i in 1 to 10 loop 	-- write numbers 1 to 10 to DATA, 1 every cycle
    DATA <= to_unsigned(i, 8);
    wait until rising_edge(CLK);
  end loop;

  -- wait until the output changes
  wait on RESULT;
  
  -- now raise ACK for clock period
  ACK <= '1';
  wait until rising_edge(CLK);
  ACK <= '0';

  -- and so on...
end process;

Also referred as standard packages.

Commercial:

• Aldec Active-HDL
• Cadence Incisive
• Mentor Graphics ModelSim
• Mentor Graphics Questa Advanced Simulator
• Synopsys VCS-MX[18]
• Xilinx Vivado Design Suite (features the Vivado Simulator)

Other:

• EDA Playground - Free web browser-based VHDL IDE (uses Synopsys VCS, Cadence Incisive, Aldec Riviera-PRO and GHDL for VHDL simulation)
• GHDL is an open source[19] VHDL compiler that can execute VHDL programs. GHDL on GitHub
• boot by freerangefactory.org is a VHDL compiler and simulator based on GHDL and GTKWave
• VHDL Simili by Symphony EDA is a free commercial VHDL simulator.
• nvc by Nick Gasson is an open source VHDL compiler[20]
• freehdl by Edwin Naroska was an open source VHDL simulator, abandoned since 2001.[21]

Notes

• Peter J. Ashenden, "The Designer's Guide to VHDL, Third Edition (Systems on Silicon)", 2008, ISBN 0-1208-8785-1. (The VHDL reference book written by one of the lead developers of the language)
• Bryan Mealy, Fabrizio Tappero (February 2012). . The no-frills guide to writing powerful VHDL code for your digital implementations. Archived from the original Free Range VHDL on 2015-02-13.
• Johan Sandstrom (October 1995). "Comparing Verilog to VHDL Syntactically and Semantically". Integrated System Design. EE Times. — Sandstrom presents a table relating VHDL constructs to Verilog constructs.
• Qualis Design Corporation (2000-07-20). "VHDL quick reference card" (PDF). 1.1. Qualis Design Corporation. Archived from the original (PDF) on 2003-12-10. {{cite journal}}: Cite journal requires |journal= (help)
• Qualis Design Corporation (2000-07-20). "1164 packages quick reference card" (PDF). 1.0. Qualis Design Corporation. Archived from the original (PDF) on 2016-03-14. {{cite journal}}: Cite journal requires |journal= (help)
• Janick Bergeron, "Writing Testbenches: Functional Verification of HDL Models", 2000, ISBN 0-7923-7766-4. (The HDL Testbench Bible)

Wikimedia Commons has media related to VHDL.

The Wikibook Programmable Logic has a page on the topic of: VHDL

• Official website
• VHDL Analysis and Standardization Group (VASG)