ARM11

In terms of instruction set, ARM11 builds on the preceding ARM9 generation. It incorporates all ARM926EJ-S features and adds the ARMv6 instructions for media support (SIMD) and accelerating IRQ response.

Microarchitecture improvements in ARM11 cores[3] include:

• SIMD instructions which can double MPEG-4 and audio digital signal processing algorithm speed
• Cache is physically addressed, solving many cache aliasing problems and reducing context switch overhead.
• Unaligned and mixed-endian data access is supported.
• Reduced heat production and lower overheating risk
• Redesigned pipeline, supporting faster clock speeds (target up to 1 GHz)
  • Longer: 8 (vs 5) stages
  • Out-of-order completion for some operations (e.g., stores)
  • Dynamic branch prediction/folding (like XScale)
  • Cache misses don't block execution of non-dependent instructions.
  • Load/store parallelism
  • ALU parallelism
• 64-bit data paths

JTAG debug support (for halting, stepping, breakpoints, and watchpoints) was simplified. The EmbeddedICE module was replaced with an interface which became part of the ARMv7 architecture. The hardware tracing modules (ETM and ETB) are compatible, but updated, versions of those used in the ARM9. In particular, trace semantics were updated to address parallel instruction execution and data transfers.

ARM makes an effort to promote recommended Verilog coding styles and techniques. This ensures semantically rigorous designs, preserving identical semantics throughout the chip design flow, which included extensive use of formal verification techniques. Without such attention, integrating an ARM11 with third-party designs could risk exposing hard-to-find latent bugs. Due to ARM cores being integrated into many different designs, using a variety of logic synthesis tools and chip manufacturing processes, the impact of its register-transfer level (RTL) quality is magnified many times.[4] The ARM11 generation focused more on synthesis than previous generations, making such concerns more of an issue.