Computational lithography

Computational lithography means the use of computers to simulate printing of micro-lithography structures. Pioneering work was done by Chris Mack at NSA in developing PROLITH, Rick Dill at IBM and Andy Neureuther at University of California, Berkeley from the early 1980s. These tools were limited to lithography process optimization as the algorithms were limited to a few square micrometres of resist. Commercial full-chip optical proximity correction (OPC), using model forms, was first implemented by TMA (now a subsidiary of Synopsys) and Numerical Technologies (also part of Synopsys) around 1997.[1]

Since then the market and complexity has grown significantly. With the move to sub-wavelength lithography at the 180 nm and 130 nm nodes, RET techniques such as Assist features, phase shift masks started to be used together with OPC. For the transition from 65 nm to 45 nm nodes customers were worrying that not only that design rules were insufficient to guarantee printing without yield limiting hotspots, but also that tape-out time may need thousands of CPUs or weeks of run time. This predicted exponential increase in computational complexity for mask synthesis on moving to the 45 nm process node spawned a significant venture capital investment in design for manufacturing start-up companies.[2]

A number of startup companies promoting their own disruptive solutions to this problem started to appear, techniques from custom hardware acceleration to radical new algorithms such as inverse lithography were touted to resolve the forthcoming bottlenecks. Despite this activity, incumbent OPC suppliers were able to adapt and keep their major customers, with RET and OPC being used together as for previous nodes, but now on more layers and with larger data files, and turn around time concerns were met by new algorithms and improvements in multi-core commodity processors. The term computational lithography was first used by Brion Technology (now a subsidiary of ASML) in 2005[3] to promote their hardware accelerated full chip lithography simulation platform. Since then the term has been used by the industry to describe full chip mask synthesis solutions. As 45 nm goes into full production and EUV lithography introduction is delayed, 32 nm and 22 nm are expected to run on existing 193 nm scanners technology.

Now, not only are throughput and capabilities concerns resurfacing, but also new computational lithography techniques such as Source Mask Optimization (SMO) is seen as a way to squeeze better resolution specific to a given design. Today, all the major mask synthesis vendors have settled on the term "computational lithography" to describe and promote the set of mask synthesis technologies required for 22 nm.

Computational lithography makes use of a number of numerical simulations to improve the performance (resolution and contrast) of cutting-edge photomasks. The combined techniques include Resolution Enhancement Technology (RET), Optical Proximity Correction (OPC), Source Mask Optimization (SMO), etc.[4] The techniques vary in terms of their technical feasibility and engineering sensible-ness, resulting in the adoption of some and the continual R&D of others.[5]

The periodic enhancement in the resolution achieved through photolithography has been a driving force behind Moore's Law. Resolution improvements enable printing of smaller geometries on an integrated circuit. The minimum feature size that a projection system typically used in photolithography can print is given approximately by:

${\displaystyle CD=k_{1}\cdot {\frac {\lambda }{NA}}}$

where

• ${\displaystyle CD}$ is the minimum feature size (also called the critical dimension).
• ${\displaystyle \lambda }$ is the wavelength of light used.
• ${\displaystyle NA}$ is the numerical aperture of the lens as seen from the wafer.
• ${\displaystyle k_{1}}$ (commonly called k1 factor) is a coefficient that encapsulates process-related factors.

Historically, resolution enhancements in photolithography have been achieved through the progression of stepper illumination sources to smaller and smaller wavelengths — from "g-line" (436 nm) and "i-line" (365 nm) sources based on mercury lamps, to the current systems based on deep ultraviolet excimer lasers sources at 193 nm. However the progression to yet finer wavelength sources has been stalled by the intractable problems associated with extreme ultraviolet lithography and x-ray lithography, forcing semiconductor manufacturers to extend the current 193 nm optical lithography systems until some form of next-generation lithography proves viable (although 157 nm steppers have also been marketed, they have proven cost-prohibitive at $50M each).[11] Efforts to improve resolution by increasing the numerical aperture have led to the use of immersion lithography. As further improvements in resolution through wavelength reduction or increases in numerical aperture have become either technically challenging or economically unfeasible, much attention has been paid to reducing the k1-factor. The k1 factor can be reduced through process improvements, such as phase-shift photomasks. These techniques have enabled photolithography at the 32 nanometer CMOS process technology node using a wavelength of 193 nm (deep ultraviolet). However, with the ITRS roadmap calling for the 22 nanometer node to be in use by 2011, photolithography researchers have had to develop an additional suite of improvements to make 22 nm technology manufacturable.[12] While the increase in mathematical modeling has been underway for some time, the degree and expense of those calculations has justified the use of a new term to cover the changing landscape: computational lithography.

• International Technology Roadmap for Semiconductors