Digital Visual Interface

Digital video pixel data is transported using multiple TMDS twisted pairs. At the electrical level, these pairs are highly resistant to electrical noise and other forms of analog distortion.

A single link DVI connection has four TMDS pairs. Three data pairs carry their designated 8-bit RGB component (red, green, or blue) of the video signal for a total of 24 bits per pixel. The fourth pair carries the TMDS clock. The binary data is encoded using 8b/10b encoding. DVI does not use packetization, but rather transmits the pixel data as if it were a rasterized analog video signal. As such, the complete frame is drawn during each vertical refresh period. The full active area of each frame is always transmitted without compression. Video modes typically use horizontal and vertical refresh timings that are compatible with cathode-ray tube (CRT) displays, though this is not a requirement. In single link mode, the maximum TMDS clock frequency is 165 MHz, which supports a maximum resolution of 2.75 megapixels (including blanking interval) at 60 Hz refresh. For practical purposes, this allows a maximum 16:10 screen resolution of 1920 × 1200 at 60 Hz.

To support higher-resolution display devices, the DVI specification contains a provision for dual link. Dual link DVI doubles the number of TMDS data pairs, effectively doubling the video bandwidth, which allows higher resolutions up to 2560 × 1600 at 60 Hz or higher refresh rates for lower resolutions.

For backward compatibility with displays using analog VGA signals, some of the contacts in the DVI connector carry the analog VGA signals.

To ensure a basic level of interoperability, DVI compliant devices are required to support one baseline display mode, "low pixel format" (640 × 480 at 60 Hz).

Like modern analog VGA connectors, the DVI connector includes pins for the display data channel (DDC), which allows the graphics adapter to read the monitor's extended display identification data (EDID). When a source and display using the DDC2 revision are connected, the source first queries the display's capabilities by reading the monitor EDID block over an I²C link. The EDID block contains the display's identification, color characteristics (such as gamma value), and table of supported video modes. The table can designate a preferred mode or native resolution. Each mode is a set of timing values that define the duration and frequency of the horizontal/vertical sync, the positioning of the active display area, the horizontal resolution, vertical resolution, and refresh rate.

The maximum length recommended for DVI cables is not included in the specification, since it is dependent on the TMDS clock frequency. In general, cable lengths up to 4.5 metres (15 ft) will work for display resolutions up to 1920 × 1200. Longer cables up to 15 metres (49 ft) in length can be used with display resolutions 1280 × 1024 or lower. For greater distances, the use of a DVI booster—a signal repeater which may use an external power supply—is recommended to help mitigate signal degradation.

• Minimum TMDS clock frequency: 25.175 MHz
  • Used for the mandatory "low pixel format" display mode: VGA (640x480) @ 60 Hz
• Maximum single link TMDS clock frequency: 165 MHz
• Single link maximum gross bit rate (including 8b/10b overhead): 4.95 Gbit/s
  • Net bit rate (subtracting 8b/10b overhead): 3.96 Gbit/s
• Dual link bit rates are twice that of single link at an identical clock frequency.
  • Gross bit rate (Including 8b/10b overhead) at a 165 MHz clock: 9.90 Gbit/s.
    • Net bit rate (subtracting 8b/10b overhead): 7.92 Gbit/s
  • Clocks above 165 MHz are allowed in dual link mode[note 1]
• Bits per pixel:
  • 24 bits per pixel support is mandatory in all resolutions supported.
  • Less than 24 bits per pixel is optional.
  • Dual link optionally supports up to 48 bits per pixel.
    • If a depth greater than 24 bits per pixel is desired, the least significant bits are sent on the second link.
• Pixels per TMDS clock cycle:
  • 1 (single link at 24 bits or less per pixel, and dual link for 25 to 48 bits per pixel) or
  • 2 (dual link at 24 bits or less per pixel)
• Example display modes (single link):
  • SXGA (1280 × 1024) @ 85 Hz with GTF blanking (159 MHz TMDS clock)
  • FHD (1920 × 1080) @ 60 Hz with CVT-RB blanking (139 MHz TMDS clock)
  • UXGA (1600 × 1200) @ 60 Hz with GTF blanking (161 MHz TMDS clock)
  • WUXGA (1920 × 1200) @ 60 Hz with CVT-RB blanking (154 MHz TMDS clock)
  • WQXGA (2560 × 1600) @ 30 Hz with CVT-RB blanking (132 MHz TMDS clock)
• Example display modes (dual link):
  • QXGA (2048 × 1536) @ 72 Hz with CVT blanking (2 pixels per 163 MHz TMDS clock)
  • FHD (1920 × 1080) @ 144 Hz[14]
  • WUXGA (1920 × 1200) @ 120 Hz with CVT-RB blanking (2 pixels per 154 MHz TMDS clock)
  • WQXGA (2560 × 1600) @ 60 Hz with CVT-RB blanking (2 pixels per 135 MHz TMDS clock)
  • WQUXGA (3840 × 2400) @ 30 Hz with CVT-RB blanking (2 pixels per 146 MHz TMDS clock)

Generalized Timing Formula (GTF) is a VESA standard which can easily be calculated with the Linux gtf utility. Coordinated Video Timings-Reduced Blanking (CVT-RB) is a VESA standard which offers reduced horizontal and vertical blanking for non-CRT based displays.[15]

One of the purposes of DVI stream encoding is to provide a DC-balanced output that reduces decoding errors. This goal is achieved by using 10-bit symbols for 8-bit or less characters and using the extra bits for the DC balancing.

Like other ways of transmitting video, there are two different regions: the active region, where pixel data is sent, and the control region, where synchronization signals are sent. The active region is encoded using transition-minimized differential signaling, where the control region is encoded with a fixed 8b/10b encoding. As the two schemes yield different 10-bit symbols, a receiver can fully differentiate between active and control regions.

When DVI was designed, most computer monitors were still of the cathode ray tube type that require analog video synchronization signals. The timing of the digital synchronization signals matches the equivalent analog ones, so the process of transforming DVI to and from an analog signal does not require extra (high-speed) memory, expensive at the time.

HDCP is an extra layer that transforms the 10-bit symbols before transmitting. Only after correct authorization can the receiver undo the HDCP encryption. Control regions are not encrypted in order to let the receiver know when the active region starts.

DVI provide one TMDS clock pair and 3 TMDS data pairs in single link mode or 6 TMDS data pairs in dual link mode. TMDS data pairs operate at a gross bit rate that is 10 times the frequency of the TMDS clock. In each TMDS clock period there is a 10-bit symbol per TMDS data pair representing 8-bits of pixel color. In single link mode each set of three 10-bit symbols represents one 24-bit pixel, while in dual link mode each set of six 10-bit symbols either represents two 24-bit pixels or one pixel of up to 48-bit color depth.

The specification document allows the data and the clock to not be aligned. However, as the ratio between the TMDS clock and gross bit rate per TMDS pair is fixed at 1:10, the unknown alignment is kept over time. The receiver must recover the bits on the stream using any of the techniques of clock/data recovery to find the correct symbol boundary. The DVI specification allows the TMDS clock to vary between 25 MHz and 165 MHz. This 1:6.6 ratio can make clock recovery difficult, as phase-locked loops, if used, need to work over a large frequency range. One benefit of DVI over other interfaces is that it is relatively straightforward to transform the signal from the digital domain into the analog domain using a video DAC, as both clock and synchronization signals are transmitted. Fixed frequency interfaces, like DisplayPort, need to reconstruct the clock from the transmitted data.

The DVI specification includes signaling for reducing power consumption. Similar to the analog VESA display power management signaling (DPMS) standard, a connected device can turn a monitor off when the connected device is powered down, or programmatically if the display controller of the device supports it. Devices with this capability can also attain Energy Star certification.

The analog section of the DVI specification document is brief and points to other specifications like VESA VSIS[16] for electrical characteristics and GTFS for timing information. The motivation for including analog is to keep compatibility with the previous VGA cables and connectors. VGA pins for HSync, Vsync and three video channels are available in both DVI-I or DVI-A (but not DVI-D) connectors and are electrically compatible, while pins for DDC (clock and data) and 5 V power and ground are kept in all DVI connectors. Thus, a passive adapter can interface between DVI-I or DVI-A (but not DVI-D) and VGA connectors.