FASTBUS

A FASTBUS system consists of one or more segments. Each segment may be a "crate segment" or a "cable segment". Segments are connected together using a segment interconnect (SI). A crate segment typically consists of a backplane with slots to hold up to 26 modules, mounted in a 19-inch rack. Each module is typically a printed circuit board with a front panel, similar to a blade PC. Modules are physically about 14 inches by 15 inches, and may occupy one or more adjacent slots.[1]

Small systems may consist of only one crate segment, or a small number of independent crate segments connected directly to a central computer rather than using segment interconnects.

FASTBUS uses the emitter coupled logic (ECL) electrical standard, which allows higher speed than TTL and generates less switching noise. Segments implement a 32-bit multiplexed address/data bus, which allows a larger address space than CAMAC. A module may be a master or slave. There may be multiple masters in a segment; masters arbitrate for control of the bus and then perform data transfers to or from slaves. This allows for very fast read-out of an entire segment by doing a chained block read from a master with a general-purpose CPU. Each I/O card will then assume mastership, send its data and then hand off mastership to the next card in a sequence, all without the overhead of the supervising board with the general-purpose CPU.

Cable Segments are implemented using 32-bit-wide parallel twisted-pair cables and a differential signalling scheme. The electrical standard allows regular ECL receiver chips but requires custom transmitter circuits which allow lines to be safely driven both high and low at the same time - this feature is required by the arbitration logic.

Full-size crates hold 26 modules.[1] Each module may dissipate up to 70 W, giving a total crate heat load of 1750 W. Modules require a −5.2 V supply for the ECL interface, usually a separate −2 V supply for ECL termination, and often a +5 V supply for TTL or CMOS logic. The FASTBUS standard also has +15 V and -15 V pins on the backplane, which are typically fed with very small power supplies as most modules use very little +/- 15 V (or any at all). Special high-capacity power supplies with large 15 V supplies would have to be used if modules drew large amounts of current on those rails. Crates typically have dedicated 200 A or 300 A switched-mode power supplies, providing current to the modules through multiple pins on the backplane connector. A large installation typically has multiple racks, each with three crates. Cooling and air handling are a significant issue, as is the safe design of high-current power distribution.

A FASTBUS crate is quite a bit taller than other types of electronics crates. The power supply for a FASTBUS crate is typically mounted below the crate, rather than being integral for the crate itself, taking up even more vertical rack space.

FASTBUS was conceived as a replacement for CAMAC in data acquisition systems. Limitations of CAMAC were a slow bus speed, limited bus width, single bus controller and unwieldy inter-crate communications (the CAMAC Branch Highway). FASTBUS sought improvement in all these areas by using a faster bus logic (ECL), an asynchronous bus protocol, and a sophisticated multi-segment design. At the time, it seemed obvious that the way to get higher speed was a wide parallel bus, since the logic for each bit was already as fast as the electronics allowed. Later developments have moved to high-speed serial protocols such as SATA, leaving designs such as the FASTBUS serial segment as a technological dead end.

The IEEE standard was originally approved in May 1984.

FASTBUS was used in many high-energy physics experiments during the 1980s, principally at laboratories involved in the development of the standard. These include CERN, SLAC, Fermilab, Brookhaven National Laboratory, and TRIUMF.

FASTBUS has now largely been replaced by VMEbus in smaller-scale systems and by custom designs (which have lower per-channel cost) in large systems.

The problems of manufacturing cable segment transmitter chips reliably, together with the cable-handling issues of the wide parallel bus, contributed to the low usage of cable segments. The system interconnect modules were also complex and expensive, again discouraging cable segment use. These problems, together with the late development of inexpensive protocol chips, hindered the expression of the full potential of FASTBUS multi-segment architecture.

FASTBUS is described in the IEEE standard 960-1986: "IEEE Standard FASTBUS Modular High-Speed Data Acquisition and Control System"

The system on which the IEEE standard is based (US Department of Energy Report DOE/ER-0189) was developed by the NIM committee of the US Department of Energy. Representatives of the ESONE committee of European laboratories and of other laboratories in Europe and Canada also contributed to the standard.