FLAGS register

The FLAGS register is the status register that contains the current state of an x86 CPU. The size and meanings of the flag bits are architecture dependent. It usually reflects the result of arithmetic operations as well as information about restrictions placed on the CPU operation at the current time. Some of those restrictions may include preventing some interrupts from triggering, prohibition of execution of a class of "privileged" instructions. Additional status flags may bypass memory mapping and define what action the CPU should take on arithmetic overflow.

The carry, parity, auxiliary carry (or half carry), zero and sign flags are included in many architectures.

In the i286 architecture, the register is 16 bits wide. Its successors, the EFLAGS and RFLAGS registers, are 32 bits and 64 bits wide, respectively. The wider registers retain compatibility with their smaller predecessors.

FLAGS
Intel x86 FLAGS register[1]
Bit #MaskAbbreviationDescriptionCategory=1=0
FLAGS
00x0001CFCarry flagStatusCY(Carry)NC(No Carry)
10x0002—Reserved, always 1 in EFLAGS [2][3]—
20x0004PFParity flagStatusPE(Parity Even)PO(Parity Odd)
30x0008—Reserved[3]—
40x0010AFAuxiliary Carry flag[4]StatusAC(Auxiliary Carry)NA(No Auxiliary Carry)
50x0020—Reserved[3]—
60x0040ZFZero flagStatusZR(Zero)NZ(Not Zero)
70x0080SFSign flagStatusNG(Negative)PL(Positive)
80x0100TFTrap flag (single step)Control
90x0200IFInterrupt enable flagControlEI(Enable Interrupt)DI(Disable Interrupt)
100x0400DFDirection flagControlDN(Down)UP(Up)
110x0800OFOverflow flagStatusOV(Overflow)NV(Not Overflow)
12-130x3000IOPLI/O privilege level (286+ only),
always all-1s on 8086 and 186		System
140x4000NTNested task flag (286+ only),
always 1 on 8086 and 186		System
150x8000MDMode flag (NEC V-series only),[5]
reserved on all Intel CPUs.
Always 1 on 8086/186, 0 on 286 and later.		Control(NEC only)
Native Mode
(186 compatible)		(NEC only)
Emulation Mode
(8080 compatible)
EFLAGS
160x0001 0000RFResume flag (386+ only)System
170x0002 0000VMVirtual 8086 mode flag (386+ only)System
180x0004 0000ACAlignment Check (486+, ring 3),
SMAP Access Check (Broadwell+, ring 0-2)		System
190x0008 0000VIFVirtual interrupt flag (Pentium+)System
200x0010 0000VIPVirtual interrupt pending (Pentium+)System
210x0020 0000IDAble to use CPUID instruction (Pentium+)System
22-290x3FC0 0000—Reserved—
300x4000 0000(none)AES key schedule loaded flag[6]
(CPUs with VIA PadLock only)		System
310x8000 0000AIAlternate Instruction Set enabled
(VIA C5XL processors only)[7]		System
RFLAGS
32‑630xFFFF FFFF…
…0000 0000		—Reserved—

Note: The mask column in the table is the AND bitmask (as hexadecimal value) to query the flag(s) within FLAGS register value.

Usage

All FLAGS registers contain the condition codes, flag bits that let the results of one machine-language instruction affect another instruction. Arithmetic and logical instructions set some or all of the flags, and conditional jump instructions take variable action based on the value of certain flags. For example, jz (Jump if Zero), jc (Jump if Carry), and jo (Jump if Overflow) depend on specific flags. Other conditional jumps test combinations of several flags.

FLAGS registers can be moved from or to the stack. This is part of the job of saving and restoring CPU context, against a routine such as an interrupt service routine whose changes to registers should not be seen by the calling code. Here are the relevant instructions:

  • The PUSHF and POPF instructions transfer the 16-bit FLAGS register.
  • PUSHFD/POPFD (introduced with the i386 architecture) transfer the 32-bit double register EFLAGS.
  • PUSHFQ/POPFQ (introduced with the x64 architecture) transfer the 64-bit quadword register RFLAGS.

In 64-bit mode, PUSHF/POPF and PUSHFQ/POPFQ are available but PUSHFD/POPFD are not.[8]: 4–349, 4–432 

The lower 8 bits of the FLAGS register is also open to direct load/store manipulation by SAHF and LAHF (load/store AH into flags).

Example

The ability to push and pop FLAGS registers lets a program manipulate information in the FLAGS in ways for which machine-language instructions do not exist. For example, the cld and std instructions clear and set the direction flag (DF), respectively; but there is no instruction to complement DF. This can be achieved with the following assembly code:

               ; This is 8086 code, with 16-bit registers pushed onto the stack,
               ; and the flags register is only 16 bits with this CPU.
pushf          ; Use the stack to transfer the FLAGS
pop   ax       ; … into the AX register
push  ax       ; and copy them back onto the stack for storage
xor   ax, 400h ; Toggle (invert, ‘complement’) the DF only; other bits are unchanged
push  ax       ; Use the stack again to move the modified value
popf           ; … into the FLAGS register
; Insert here the code that required the DF flag to be complemented
popf          ; Restore the original value of the FLAGS

By manipulating the FLAGS register, a program can determine the model of the installed processor. For example, the alignment flag can only be changed on the 486 and above. If the program tries to modify this flag and senses that the modification did not persist, the processor is earlier than the 486.

Starting with the Intel Pentium, the CPUID instruction reports the processor model. However, the above method remains useful to distinguish between earlier models.

See also

References
  1. Intel 64 and IA-32 Architectures Software Developer's Manual (PDF). Vol. 1. May 2012. pp. 3–21.
  2. Intel 64 and IA-32 Architectures Software Developer’s Manual (PDF). Vol. 1. Dec 2016. p. 78.
  3. "Silicon reverse engineering: The 8085's undocumented flags". www.righto.com. Retrieved 2018-10-21.
  4. Intel 64 and IA-32 Architectures Software Developer’s Manual, Vol. 1. Dec 2022. p. 3-16.
  5. NEC, 16-bit V-Series User's Manual, document no. U11301E, sep 2000, p. 186
  6. VIA, PadLock Programming Guide, v1.66, Aug 4, 2005, pp. 7-8. Archived from the original on May 26, 2010.
  7. VIA, VIA C3 Processor Alternate Instruction Set Application Note, version 0.24, 2002 - see figure 2 on page 12 and chapter 4 on page 21 for details on the EFLAGS.AI flag.
  8. Intel 64 and IA-32 Architectures Software Developer’s Manual (PDF). Vol. 2B. May 2012.
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