Icarus Verilog
Icarus Verilog is an implementation of the Verilog hardware description language compiler that generates netlists in the desired format (EDIF). It supports the 1995, 2001 and 2005 versions of the standard, portions of SystemVerilog, and some extensions.
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| Developer(s) | Stephen Williams |
|---|---|
| Stable release | 11.0
/ 12 October 2020 |
| Repository | |
| Written in | C++ |
| Operating system | Linux, FreeBSD, OpenSolaris, AIX, Microsoft Windows, and Mac OS X |
| Platform | Cross-platform |
| Available in | English |
| Type | Verilog Simulator |
| License | GPL-2.0-or-later |
| Website | http://iverilog.icarus.com/ |
Icarus Verilog is available for Linux, FreeBSD, OpenSolaris, AIX, Microsoft Windows, and Mac OS X. Released under the GNU General Public License, Icarus Verilog is free software.
As of release 0.9, Icarus is composed of a Verilog compiler (including a Verilog preprocessor) with support for plug-in backends, and a virtual machine that simulates the design. Release v10.0, besides general improvements and bug fixes, added preliminary support for VHDL, but the VHDL support has been abandoned as of 2018.
History
Not even the author quite remembers when the project was first started, but CVS records go back to 1998. There have been releases 0.2 through the current stable release 10.0.
Icarus Verilog development is done largely by the sole regular author, Stephen Williams. Some non-trivial portions have been contributed as accepted patches.
See also
External links
- Icarus Verilog official web site
- GitHub page
- Icarus Verilog documentation web site
- Icarus Verilog installer for Microsoft Windows
- Online interface to Icarus Verilog
- Open Source in Electronic Design Automation
- Icarus Verilog: Open-Source Verilog More than a Year Later
- EDA Playground - run Icarus Verilog simulations from the web browser
- Historical CSV repository
- VHDL support abandoned