Intel 82497
The Intel 82497 is a Cache Controller for the P5 Pentium processor that was developed by Intel in the mid-1990s. It works with multiple 82492 Cache SRAMs. It was part of the Intel 824xx family of processors, which were designed for use in high-performance computer systems and servers. The 82497 was a high-end processor that was used in a number of high-end servers and workstations. It was based on the Pentium Pro architecture and was manufactured using a 0.35 micron process. It had a clock speed of up to 200 MHz and was available in a number of different configurations, including versions with one, two, or four processors. One of the main features of the 82497 was its support for multiprocessing, which allowed it to be used in systems with multiple processors. This made it well-suited for use in high-performance computing environments, where it could be used to handle demanding workloads such as scientific simulations and data analysis. Overall, the Intel 82497 was a powerful and sophisticated processor that was used in a number of high-end computer systems during the mid-1990s. It helped to pave the way for the development of more advanced processors in the years that followed.
Technical description
The 82497 Cache Controller implements the MESI write-back protocol for full multiprocessing support. Dual ported buffers and registers allow the 82497 to concurrently handle CPU bus, memory bus, and internal cache operation for maximum performance.
The 82497 Cache Controller with multiple 82492 Cache SRAMs combine with the Pentium processor (735\90,815\100, 1000\120, 1110\133) to form a CPU cache chip set designed for high performance servers and function-rich desktops. The high-speed interconnect between the CPU and cache components has been optimized to provide zero-wait state operation. This CPU cache chip set is fully compatible with existing software, and has data integrity features for mission critical applications.
The 82497 Cache Controller implements the MESI write-back protocol for full multiprocessing support. Dual ported buffers and registers allow the 82497 to concurrently handle CPU bus, memory bus, and internal cache operation for maximum performance. The 82492 is a customized high performance SRAM that supports 32-, 64-, and 128-bit wide memory bus widths, 16-, 32-, and 64-byte line sizes, and optional sectoring. The data path between the CPU bus and the memory bus is separated by the 82492, allowing the CPU bus to handshake synchronously, asynchronously, or with a strobed protocol, and allowing concurrent CPU bus and memory bus operations.
References
- Pentium Processor Family Developer’s Manual Volume 2: 82496/82497/82498 Cache Controller and 82491/82492/82493 Cache SRAM