I²S

This standard was introduced in 1986 by Philips Semiconductor (now NXP Semiconductors) and was first revised June 5, 1996.[1] The standard was last revised on February 17, 2022 and updated terms master and slave to controller and target.[2]

Timing diagram of I²S

The I²S protocol outlines one specific type of PCM digital audio communication with defined parameters outlined in the Philips specification.

The bus consists of at least three lines:

1. Bit clock line
   • Officially "continuous serial clock (SCK)".[1] Typically written "bit clock (BCLK)".[3]
2. Word clock line
   • Officially "word select (WS)".[1] Typically called "left-right clock (LRCLK)"[3] or "frame sync (FS)".[4]
   • 0 = Left channel, 1 = Right channel[1]
3. At least one multiplexed data line
   • Officially "serial data (SD)",[1] but can be called SDATA, SDIN, SDOUT, DACDAT, ADCDAT, etc.[3]

It may also include the following lines:

1. Master clock (typically 256 x LRCLK)
   • This is not part of the I2S standard,[5] but is commonly included for synchronizing the internal operation of the analog/digital converters.[4][6]
2. A multiplexed data line for upload

The bit clock pulses once for each discrete bit of data on the data lines. The bit clock frequency is the product of the sample rate, the number of bits per channel and the number of channels. So, for example, CD Audio with a sample frequency of 44.1 kHz, with 16 bits of precision and two channels (stereo) has a bit clock frequency of:

44.1 kHz × 16 × 2 = 1.4112 MHz

The word select clock lets the device know whether channel 0 or channel 1 is currently being sent, because I²S allows two channels to be sent on the same data line. It is a 50% duty-cycle signal that has the same frequency as the sample frequency. For stereo material, the I²S specification states that left audio is transmitted on the low cycle of the word select clock and the right channel is transmitted on the high cycle. It is typically synchronized to the falling edge of the serial clock, as the data is latched on the rising edge.[1] The word select clock changes one bit clock period before the MSB is transmitted. This enables, for example, the receiver to store the previous word and clear the input for the next.[1]

Data is signed, encoded as two's complement with the MSB (most significant bit) first.[1] This allows the number of bits per frame to be arbitrary, with no negotiation required between transmitter and receiver.[1]

In audio equipment, I²S is sometimes used as an external link between a CD player or digital audio streaming device and an external digital-to-analog converter, as opposed to a purely internal connection within one player box. This may form an alternative to the commonly used AES/EBU, Toslink or S/PDIF standards.

The I²S connection was not intended to be used via cables, and most integrated circuits will not have the correct impedance for coaxial cables. As the impedance adaptation error associated with the different line lengths can cause differences in propagation delay between the clock line and data line, this can result in synchronization problems between the SCK, WS and data signals, mainly at high sampling frequencies and bitrates. As the I²S bus doesn't have any error detection mechanism, this can cause significant decoding errors.

There is no standard interconnecting cable for this application. Some manufacturers simply provide three BNC connectors, an 8P8C ("RJ45") socket or a DE-9 connector. Others like Audio Alchemy (now defunct) used DIN connectors. PS Audio, Musica Pristina and Wyred4Sound use an HDMI connector.[7] Dutch manufacturer Van Medevoort has implemented Q-link in some of its equipment, which transfers I²S over 4 RCA connectors (data, MCK, LRCK, BCK).

• SPI bus
• S/PDIF

• I²S Specification - Philips/NXP
• I²S and STM32F4 Slides - Auburn University
• Common inter-IC digital interfaces for audio data transfer, PDF