Zilog Z80000

The Z80000 is Zilog's 32-bit processor, first released in 1986. It is essentially a 32-bit expansion of its 16-bit predecessor, the Zilog Z8000. It includes multiprocessing capability, a six-stage instruction pipeline, and a 256-byte cache. Its memory addressing system can access 4 gigabytes of RAM. It can execute code written for the Z8000, but is not compatible with the Z80.

Described at the time as a "mainframe on a chip", the processor is in many ways an equivalent to Intel's 80386. Delays in the initial manufacturing pushed back its availability date to after that of the 386, and the Z80000 saw little use in the market.

Description

Like the Z8000 it is based on, the Z80000 has sixteen general-purpose registers, but expanded from the Z8000's 16-bit to 32-bit. Like the Z8000, the Z80000 allows its registers to be combined, in this case using two 32-bit registers to act as a single 64-bit one. To support the Z8000s 16-bit wide data, the Z80000 can place two 16-bit values in a single 32-register.

The processor includes a memory management unit that provides protected memory, important for multitasking, and virtual memory addressing for temporary storage of RAM on a hard disk. The processor has three methods of accessing memory:

  • compact mode – meant for small programs, could only access 64 KB (16-bit addresses, equivalent to the Z8000's non-segmented mode). Address bits 31-16 of all virtual addresses comes from address bits 31-16 of the program counter.
  • segmented mode – 32,768 segments of 64 KB (16-bit address; comprising memory from 0-2GB) and 128 segments of 16 MB (24-bit address; comprising memory from 2GB-4GB), making a total of 4 GB (32-bit address) of accessible memory.
  • linear mode – direct 4 GB (32-bit address) accessible memory

The processor is designed to interoperate with other integrated circuits designed for use with the Z8000, such as the Zilog Z8070 floating-point coprocessor.

The Z320 was the CMOS version of the Z80000.

Linear vs. Segmented Addressing

Linear addresses used the complete result of any address computations, and so could address any part of memory without restriction.

Segmented addresses restrict effective address computations to the specified segment of the base pointer register. For example, if RR2 contained the value 0x10002000 (byte offset 0x2000 of small segment 4096), and you wanted to access a byte offset 0xE000 from this pointer, the final effective address would be 0x10000000, as the wrap-around into higher address bits is prevented. Base address bit 31 selects whether 64KiB segments (0) or 16MiB segments (1) are used. Note that the base address register (not index registers!) determines the segment size and number.

Segment in this case refers not to an Intel-style segment, but to a Unix-style segment.

References
    • Zilog Z80,000 CPU Preliminary Technical Manual (PDF). San Jose, California: Zilog. September 1984. Retrieved 2017-01-19.


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