Larrabee (microarchitecture)

Larrabee was intended to differ from older discrete GPUs such as the GeForce 200 Series and the Radeon 4000 series in three major ways:

• It was to use the x86 instruction set with Larrabee-specific extensions.[14]
• It was to feature cache coherency across all its cores.[14]
• It was to include very little specialized graphics hardware, instead performing tasks like z-buffering, clipping, and blending in software, using a tile-based rendering approach.[14]

This had been expected to make Larrabee more flexible than current GPUs, allowing more differentiation in appearance between games or other 3D applications. Intel's SIGGRAPH 2008 paper mentioned several rendering features that were difficult to achieve on current GPUs: render target read, order-independent transparency, irregular shadow mapping, and real-time raytracing.[14]

More recent GPUs such as ATI's Radeon HD 5xxx and Nvidia's GeForce 400 Series feature increasingly broad general-purpose computing capabilities via DirectX11 DirectCompute and OpenCL, as well as Nvidia's proprietary CUDA technology, giving them many of the capabilities of Larrabee.

The x86 processor cores in Larrabee differed in several ways from the cores in current Intel CPUs such as the Core 2 Duo or Core i7:

• Its x86 cores were based on the much simpler P54C Pentium design which is still being maintained for use in embedded applications.[15] The P54C-derived core is superscalar but does not include out-of-order execution, though it has been updated with modern features such as x86-64 support,[14] similar to the Bonnell microarchitecture used in Atom. In-order execution means lower performance for individual cores, but since they are smaller, more can fit on a single chip, increasing overall throughput. Execution is also more deterministic so instruction and task scheduling can be done by the compiler.
• Each core contained a 512-bit vector processing unit, able to process 16 single precision floating point numbers at a time. This is similar to, but four times larger than, the SSE units on most x86 processors, with additional features like scatter/gather instructions and a mask register designed to make using the vector unit easier and more efficient. Larrabee was to derive most of its number-crunching power from these vector units.[14]
• It included one major fixed-function graphics hardware feature: texture sampling units. These perform trilinear and anisotropic filtering and texture decompression.[14]
• It had a 1024-bit (512-bit each way) ring bus for communication between cores and to memory.[14] This bus can be configured in two modes to support Larrabee products with 16 cores or more, or fewer than 16 cores.[16]
• It included explicit cache control instructions to reduce cache thrashing during streaming operations which only read/write data once.[14] Explicit prefetching into L2 or L1 cache is also supported.
• Each core supported four-way interleaved multithreading, with four copies of each processor register.[14]

Theoretically Larrabee's x86 processor cores would have been able to run existing PC software, or even operating systems. A different version of the processor might sit in motherboard CPU sockets using QuickPath,[17] but Intel never announced any plans for this. Though Larrabee's native C/C++ compiler included auto-vectorization and many applications were able to execute correctly after having been recompiled, maximum efficiency was expected to have required code optimization using C++ vector intrinsics or inline Larrabee assembly code.[14] However, as in all GPGPUs, not all software would have benefited from utilization of a vector processing unit. One tech journalism site claims that Larrabee's graphics capabilities were planned to be integrated in CPUs based on the Haswell microarchitecture.[18]

Larrabee's philosophy of using many small, simple cores was similar to the ideas behind the Cell processor. There are some further commonalities, such as the use of a high-bandwidth ring bus to communicate between cores.[14] However, there were many significant differences in implementation which were expected to make programming Larrabee simpler.

• The Cell processor includes one main processor which controls many smaller processors. Additionally, the main processor can run an operating system. In contrast, all of Larrabee's cores are the same, and the Larrabee was not expected to run an OS.
• Each computer core in the Cell (SPE) has a local store, for which explicit (DMA) operations are used for all accesses to DRAM. Ordinary reads and writes to DRAM are not allowed. In Larrabee, all on-chip and off-chip memories are under automatically managed coherent cache hierarchy, so that its cores virtually shared a uniform memory space through standard copy (MOV) instructions. Larrabee cores each had 256 KB of local L2 cache, and an access which hits another L2 segment takes longer to access.[14]
• Because of the cache coherency noted above, each program running in Larrabee had virtually a large linear memory just as in traditional general-purpose CPU; whereas an application for Cell should be programmed taking into consideration limited memory footprint of the local store associated with each SPE (for details see this article) but with theoretically higher bandwidth. However, since local L2 is faster to access, an advantage can still be gained from using Cell-style programming methods.
• Cell uses DMA for data transfer to and from on-chip local memories, which enables explicit maintenance of overlays stored in local memory to bring memory closer to the core and reduce access latencies, but requiring additional effort to maintain coherency with main memory; whereas Larrabee used a coherent cache with special instructions for cache manipulation (notably cache eviction hints and pre-fetch instructions), which mitigated miss and eviction penalties and reduce cache pollution (e.g. for rendering pipelines and other stream-like computation) at the cost of additional traffic and overhead to maintain cache coherency.[14]
• Each compute core in the Cell runs only one thread at a time, in-order. A core in Larrabee ran up to four threads, but only one at a time. Larrabee's hyperthreading helped hide the latencies inherent to in-order execution.

Intel began integrating a line of GPUs onto motherboards under the Intel GMA brand in 2004. Being integrated onto motherboards (newer versions, such as those released with Sandy Bridge, are incorporated onto the same die as the CPU) these chips were not sold separately. Though the low cost and power consumption of Intel GMA chips made them suitable for small laptops and less demanding tasks, they lack the 3D graphics processing power to compete with contemporary Nvidia and AMD/ATI GPUs for a share of the high-end gaming computer market, the HPC market, or a place in popular video game consoles. In contrast, Larrabee was to be sold as a discrete GPU, separate from motherboards, and was expected to perform well enough for consideration in the next generation of video game consoles.[19][20]

The team working on Larrabee was separate from the Intel GMA team. The hardware was designed by a newly formed team at Intel's Hillsboro, Oregon, site, separate from those that designed the Nehalem. The software and drivers were written by a newly formed team. The 3D stack specifically was written by developers at RAD Game Tools (including Michael Abrash).[21]

The Intel Visual Computing Institute will research basic and applied technologies that could be applied to Larrabee-based products.[22]