Subtractor

Figure 1 :Logic diagram for a half subtractor

The half subtractors can be designed through the combinational Boolean logic circuits ^[2] as shown in Figure 1 and 2.The half subtractor is a combinational circuit which is used to perform subtraction of two bits. It has two inputs, the minuend ${\displaystyle X}$ and subtrahend ${\displaystyle Y}$ and two outputs the difference ${\displaystyle D}$ and borrow out ${\displaystyle B_{\text{out}}}$. The borrow out signal is set when the subtractor needs to borrow from the next digit in a multi-digit subtraction. That is, ${\displaystyle B_{\text{out}}=1}$ when ${\displaystyle X<Y}$. Since ${\displaystyle X}$ and ${\displaystyle Y}$ are bits, ${\displaystyle B_{\text{out}}=1}$ if and only if ${\displaystyle X=0}$ and ${\displaystyle Y=1}$. An important point worth mentioning is that the half subtractor diagram aside implements ${\displaystyle X-Y}$ and not ${\displaystyle Y-X}$ since ${\displaystyle B_{\text{out}}}$ on the diagram is given by

${\displaystyle B_{\text{out}}={\overline {X}}\cdot Y}$.

This is an important distinction to make since subtraction itself is not commutative, but the difference bit ${\displaystyle D}$ is calculated using an XOR gate which is commutative.

Figure 2: Half-subtractor using NAND gate only.

The truth table for the half subtractor is:

Using the table above and a Karnaugh map, we find the following logic equations for ${\displaystyle D}$ and ${\displaystyle B_{\text{out}}}$:

${\displaystyle D=X\oplus Y}$

${\displaystyle B_{\text{out}}={\overline {X}}\cdot Y}$.

Consequently, a simplified half-subtract circuit, advantageously avoiding crossed traces in particular as well as a negate gate is:

      X ── XOR ─┬─────── |X-Y|,  is 0 if X equals Y, 1 otherwise
         ┌──┘   └──┐  
      Y ─┴─────── AND ── borrow, is 1 if Y > X, 0 otherwise

where lines to the right are outputs and others (from the top, bottom or left) are inputs.

The full subtractor is a combinational circuit which is used to perform subtraction of three input bits: the minuend ${\displaystyle X}$, subtrahend ${\displaystyle Y}$, and borrow in ${\displaystyle B_{\text{in}}}$. The full subtractor generates two output bits: the difference ${\displaystyle D}$ and borrow out ${\displaystyle B_{\text{out}}}$. ${\displaystyle B_{\text{in}}}$ is set when the previous digit is borrowed from ${\displaystyle X}$. Thus, ${\displaystyle B_{\text{in}}}$ is also subtracted from ${\displaystyle X}$ as well as the subtrahend ${\displaystyle Y}$. Or in symbols: ${\displaystyle X-Y-B_{\text{in}}}$. Like the half subtractor, the full subtractor generates a borrow out when it needs to borrow from the next digit. Since we are subtracting ${\displaystyle Y}$ and ${\displaystyle B_{\text{in}}}$ from ${\displaystyle X}$, a borrow out needs to be generated when ${\displaystyle X<Y+B_{\text{in}}}$. When a borrow out is generated, 2 is added in the current digit. (This is similar to the subtraction algorithm in decimal. Instead of adding 2, we add 10 when we borrow.) Therefore, ${\displaystyle D=X-Y-B_{\text{in}}+2B_{\text{out}}}$.

The truth table for the full subtractor is:

Therefore the equation is:

${\displaystyle D=X\oplus Y\oplus B_{in}}$

${\displaystyle B_{out}={\bar {X}}B_{in}+{\bar {X}}Y+YB_{in}}$

• Adder (electronics)
• Carry-lookahead adder
• Carry-save adder
• Adding machine
• Adder-subtractor

1. Foundations Of Digital Electronics by Elijah Mwangi
2. Beltran, A.A., Nones, K., Salanguit, R.L., Santos, J.B., Santos, J.M., & Dizon, K.J. (2021). Low Power NAND Gate–based Half and Full Adder / Subtractor Using CMOS Technique.

• N bit Binary addition or subtraction using single circuit.