Torrenza

Torrenza was an initiative announced by Advanced Micro Devices (AMD) in 2006 to improve support for the integration of specialized coprocessors in systems based on AMD Opteron microprocessors. Torrenza does not refer to a specific product or specific technology, though the primary focus is on the integration of coprocessor devices directly connected to the Opteron processors' HyperTransport links, and other co-processors connected via PCI Express. The initiative's stated goals include improving technical and technology support for third-party developers of coprocessing devices, reducing the cost of implementing HyperTransport interfaces on these devices, and improving the performance of the integrated system. It can be argued, that the original idea behind Torrenza was successfully implemented in form of Heterogeneous System Architecture by AMD and the other members of the HSA Foundation.

Goals

AMD expected tightly-integrated coprocessor technology to be a proving ground for developing and assessing technologies that may eventually migrate onto the processor die itself. Promoting third-party co-processors was envisioned as a stepping stone to the advanced CPU designs of the future and a platform for software development needed for those hardware designs. On June 1, 2006, AMD announced the Torrenza program.[1]

The Torrenza label was applied to both accelerator projects that pre-dated the announcement as well as projects announced later. Intel followed suit by opening up its front side bus to third-party companies,[2] alongside a PCI Express extension project jointly co-developed with IBM codenamed Geneseo.

On September 21, 2006, AMD announced expanded support for the program. Companies includes Cray, Fujitsu Siemens Computers, IBM, Sun Microsystems, Dell, Tarari and Hewlett-Packard.[3] The program web site existed through 2008.[4]

Technology

HyperTransport-connected devices can be installed in HTX slots or in Opteron CPU sockets. HTX slots are placed to allow access to external cabling and so are the natural location for network devices, such as the Qlogic Infinipath network adapter. As an alternative installation location, AMD CPU sockets provide access to the motherboard DRAM channels and support a larger power budget with room for the corresponding heat sink. In some system configurations, the CPU sockets provide access to multiple HyperTransport links that support higher frequencies than single 16-bit (per direction) 800 MHz link supported by the HTX slot.

Examples of devices that can be installed in AMD Opteron CPU sockets included field-programmable gate array (FPGA) co-processor modules. These fit in Socket 940 dual-socket motherboards and are based on Xilinx and Altera devices. They use HyperTransport to directly connect the FPGA devices to the other CPU socket and both provide memory controllers to access memory on the motherboard. An accelerator card for offloading antivirus search was another example.[5]

Torrenza was closely (though not exclusively) identified with HyperTransport technology promoted by the HyperTransport Consortium. AMD is a supporter and partner of the OpenFPGA Consortium. Technology elements of Torrenza were related to the AMD Fusion, later Accelerated Processing Unit, project, which targets the integration of graphics processing units (or other coprocessing functions) and CPU cores onto one chip. As a programmatic distinction, Torrenza refers to external acceleration technology (including graphics processing units in PCIe slots), while Fusion refers to integrated acceleration technology. It was rumored in 2007 that the future IBM POWER7 processors would be socket compatible with Opteron processors.[6] The IBM Roadrunner supercomputer connected thousands of Opteron cores to almost as many Cell Broadband Engines in an effort to reach 1 petaflop of processing power. However, it is not clear if this system configuration should be considered an example of a coprocessing architecture because the Opteron and Cell processors run independent operating systems and communicate using software-based message-passing protocols. Delivered in mid-2008, AMD was not expected to emphasize the Torrenza initiative from about that time.[7] It was not mentioned in a 2009 news release about the Roadrunner, for example.[8]

See also

References
  1. "AMD Announces Initiatives To Elevate AMD64 As Platform For System- And Industry-Wide Innovation". News release. Advanced Micro Devices. June 1, 2006. Archived from the original on June 13, 2006. Retrieved May 29, 2011.
  2. Ashlee Vance (April 17, 2007). "High fiber diet gives Intel 'regularity' needed to beat AMD". The Register. Retrieved May 28, 2011.
  3. "AMD Announces Socket Compatibility Plans to Drive Industry Collaboration". News release. Advanced Micro Devices. September 21, 2006. Archived from the original on October 10, 2006. Retrieved May 29, 2011.
  4. "AMD's Torrenza Initiative: Creating a Community of Collaboration". Initiative web site. Advanced Micro Devices. Archived from the original on May 11, 2008. Retrieved May 29, 2011.
  5. Wolfgang Gruener (April 29, 2007). "AMD's Torrenza evolves into first real world applications". TG Daily. Retrieved May 29, 2011.
  6. "IBM Power 7 to be Opteron socket compatible: Mini Update While Big Blue pursues Itanium FUD campaign". The Inquirer.net. March 25, 2007. Archived from the original on August 27, 2009. Retrieved May 29, 2011.{{cite news}}: CS1 maint: unfit URL (link)
  7. Wolfgang Gruener (June 8, 2008). "Roadrunner: 130,536 cores break the Petaflop barrier". TG Daily. Retrieved May 29, 2011.
  8. "Most Powerful Supercomputer in the World Powered by the Six-Core AMD Opteron™ Processor". News release. Advanced Micro Devices. November 16, 2009. Retrieved May 29, 2011.
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