Zen 4

Like its predecessor, Zen 4 in its Desktop Ryzen variants features one or two Core Complex Dies (CCDs) built on TSMC's 5 nm process and one I/O die built on 6 nm.[8][9] Previously, the I/O die on Zen 3 was built on GlobalFoundries' 14 nm process for EPYC and 12 nm process for Ryzen. Zen 4's I/O die includes integrated RDNA 2 graphics for the first time on any Zen architecture. Zen 4 marks the first utilization of the 5 nm process for x86-based desktop processors.

On desktop and server platforms, Zen 4 supports only DDR5 memory, with support for DDR4 dropped. Additionally, Zen 4 supports new AMD EXPO SPD profiles for more comprehensive memory tuning and overclocking by the RAM manufacturers. Unlike Intel XMP, AMD EXPO is marketed as an open, license and royalty-free standard for describing memory kit parameters, such as operating frequency, timings and voltages. It allows to encode a wider set of timings to achieve better performance and compatibility. However, XMP memory profiles are still supported.[10] EXPO can also support Intel processors.[11]

All Ryzen desktop processors feature 28 (24 + 4) PCIe 5.0 lanes. This means that a discrete GPU can be connected by 16 PCIe lanes or two GPUs by 8 PCIe lanes each. Additionally, there are now 2 x 4 lane PCIe interfaces, most often used for M.2 storage devices. Whether the lanes connecting the GPUs in the mechanical x16 slots are executed as PCIe 4.0 or PCIe 5.0 can be configured by the mainboard manufacturers. Finally, 4 PCIe 5.0 lanes are reserved for connecting the south bridge chip or chipset.

Zen 4 is the first AMD microarchitecture to support AVX-512 instruction set extension. Most 512-bit vector instructions are split in two and executed by the 256-bit SIMD execution units internally. The two halves execute in parallel on a pair of execution units and are still tracked as a single micro-OP (except for stores), which means the execution latency isn't doubled compared to 256-bit vector instructions. There are four 256-bit execution units, which gives a maximum throughput of two 512-bit vector instructions per clock cycle, e.g. one multiplication and one addition. The maximum number of instructions per clock cycle is doubled for vectors of 256 bits or less. Load and store units are also 256 bits each, retaining the throughput of up to two 256-bit loads or one store per cycle that was supported by Zen 3. This translates to up to one 512-bit load per cycle or one 512-bit store per two cycles.[10][12][13]

Other features and improvements, compared to Zen 3, include:[10][12]

• L1 Branch Target Buffer (BTB) size increased by 50%, to 1.5K entries. Each entry is now able to store up to two branch targets, provided that the first branch is a conditional branch and the second branch is located within the same aligned 64-byte cache line as the first one.
• L2 BTB increased to 7K entries.
• Improved direct and indirect branch predictors.
• OP cache size increased by 68%, to 6.75K OPs. The OP cache is now able to produce up to 9 macro-OPs per cycle (up from 6).
• Re-order buffer (ROB) is increased by 25%, to 320 instructions.
• Integer register file increased to 224 registers, FP/vector register file increased to 192 registers. FP/vector register file widened to 512 bits to support AVX-512. Added a new mask register file, capable of storing 68 mask registers.
• Load queue size increased by 22%, to 88 pending loads.
• L2 cache is doubled, from 512 KiB to 1 MiB per core, 8-way.
• Automatic IBRS, where indirect branch restricted speculation mode is automatically enabled and disabled when control enters and leaves Ring 0 (kernel mode). This reduces the cost of user/kernel mode transitions.
• ~13% IPC increase on average.
• Up to 5.7 GHz max core frequency.
• Memory speeds up to DDR5-5200 are officially supported.
• In Ryzen 7000 desktop processors, the integrated GPU contains two RDNA 2 Compute Units running at up to 2.2 GHz.

Zen 4c is a variant of Zen 4 featuring smaller Zen 4 cores with lower clock frequencies, power usage, reduced L3 cache per core, and is intended to fit a greater number of cores in a given space.

Zen 4c is used for AMD's lineup of Bergamo Epyc 97x4 CPUs, launched June 13th, 2023.[24] Bergamo features up to 128 cores and 256 threads.[25] Zen 4c is also used in Siena, AMD's codename for its Epyc 8004 series of CPUs designed for edge computing, telecommunications, and other server segments where lower costs and higher energy efficiency are a priority over performance. Siena has up to 64 cores and 128 threads, and was released on September 18, 2023.[26] Zen 4c's smaller cores and higher core counts are designed for heavily multi-threaded workloads such as cloud computing.[27][28]