AMD APU

AMD Accelerated Processing Unit (APU), formerly known as Fusion, is a series of 64-bit microprocessors from Advanced Micro Devices (AMD), combining a general-purpose AMD64 central processing unit (CPU) and 3D integrated graphics processing unit (IGPU) on a single die.

AMD APU
A-series APU
Release date2011 (Original); 2017 (Zen based)
CodenameFusion
Desna
Ontario
Zacate
Llano
Hondo
Trinity
Weatherford
Richland
Kaveri
Godavari
Kabini
Temash
Carrizo
Bristol Ridge
Raven Ridge
Picasso
Renoir
Cezanne
IGP
Wrestler
WinterPark
BeaverCreek
ArchitectureAMD64
Models
Cores1 to 8
Transistors
  • 32 nm 1.178B (Llano)
  • 32 nm 1.303B (Trinity)
  • 32 nm 1.3B (Richland)
  • 28 nm 2.41B (Kaveri)
  • 14 nm 4.95B (Raven Ridge)
  • 12 nm (Picasso)
  • 7 nm (Renoir & Cezanne)
  • 6 nm (Rembrandt)
API support
Direct3DDirect3D 11
Direct3D 12
OpenCL1.2
OpenGL4.1+
History
PredecessorAthlon II
SuccessorRyzen

AMD announced the first generation APUs, Llano for high-performance and Brazos for low-power devices, in January 2011. The second generation Trinity for high-performance and Brazos-2 for low-power devices were announced in June 2012. The third generation Kaveri for high performance devices were launched in January 2014, while Kabini and Temash for low-power devices were announced in the summer of 2013. Since the launch of the Zen microarchitecture, Ryzen and Athlon APUs have released to the global market as Raven Ridge on the DDR4 platform, after Bristol Ridge a year prior.

AMD has also supplied semi-custom APUs for consoles starting with the release of Sony PlayStation 4 and Microsoft Xbox One eighth generation video game consoles.

History

The AMD Fusion project started in 2006 with the aim of developing a system on a chip that combined a CPU with a GPU on a single die. This effort was moved forward by AMD's acquisition of graphics chipset manufacturer ATI[1] in 2006. The project reportedly required three internal iterations of the Fusion concept to create a product deemed worthy of release.[1] Reasons contributing to the delay of the project include the technical difficulties of combining a CPU and GPU on the same die at a 45 nm process, and conflicting views on what the role of the CPU and GPU should be within the project.[2]

The first generation desktop and laptop APU, codenamed Llano, was announced on 4 January 2011 at the 2011 Consumer Electronics Show in Las Vegas and released shortly thereafter.[3][4] It featured K10 CPU cores and a Radeon HD 6000 series GPU on the same die on the FM1 socket. An APU for low-power devices was announced as the Brazos platform, based on the Bobcat microarchitecture and a Radeon HD 6000 series GPU on the same die.[5]

At a conference in January 2012, corporate fellow Phil Rogers announced that AMD would re-brand the Fusion platform as the Heterogeneous System Architecture (HSA), stating that "it's only fitting that the name of this evolving architecture and platform be representative of the entire, technical community that is leading the way in this very important area of technology and programming development."[6] However, it was later revealed that AMD had been the subject of a trademark infringement lawsuit by the Swiss company Arctic, who used the name "Fusion" for a line of power supply products.[7]

The second generation desktop and laptop APU, codenamed Trinity was announced at AMD's 2010 Financial Analyst Day[8][9] and released in October 2012.[10] It featured Piledriver CPU cores and Radeon HD 7000 series GPU cores on the FM2 socket.[11] AMD released a new APU based on the Piledriver microarchitecture on 12 March 2013 for Laptops/Mobile and on 4 June 2013 for desktops under the codename Richland.[12] The second generation APU for low-power devices, Brazos 2.0, used exactly the same APU chip, but ran at higher clock speed and rebranded the GPU as Radeon HD 7000 series and used a new I/O controller chip.

Semi-custom chips were introduced in the Microsoft Xbox One and Sony PlayStation 4 video game consoles,[13][14] and subsequently in the Microsoft Xbox Series X|S and Sony PlayStation 5 consoles.

A third generation of the technology was released on 14 January 2014, featuring greater integration between CPU and GPU. The desktop and laptop variant is codenamed Kaveri, based on the Steamroller architecture, while the low-power variants, codenamed Kabini and Temash, are based on the Jaguar architecture.[15]

Since the introduction of Zen-based processors, AMD renamed their APUs as the Ryzen with Radeon Graphics and Athlon with Radeon Graphics, with desktop units assigned with G suffix on their model numbers (e.g. Ryzen 5 3400G & Athlon 3000G) to distinguish them from regular processors or with basic graphics and also to differentiate away from their former Bulldozer era A-series APUs. The mobile counterparts were always paired with Radeon Graphics regardless of suffixes.

In November 2017, HP released the Envy x360, featuring the Ryzen 5 2500U APU, the first 4th generation APU, based on the Zen CPU architecture and the Vega graphics architecture.[16]

Features

Heterogeneous System Architecture
Main article: Heterogeneous System Architecture

AMD is a founding member of the Heterogeneous System Architecture (HSA) Foundation and is consequently actively working on developing HSA in cooperation with other members. The following hardware and software implementations are available in AMD's APU-branded products:

TypeHSA featureFirst implementedNotes
Optimized PlatformGPU Compute C++ Support2012
Trinity APUs		Support OpenCL C++ directions and Microsoft's C++ AMP language extension. This eases programming of both CPU and GPU working together to process support parallel workloads.
HSA-aware MMUGPU can access the entire system memory through the translation services and page fault management of the HSA MMU.
Shared Power ManagementCPU and GPU now share the power budget. Priority goes to the processor most suited to the current tasks.
Architectural IntegrationHeterogeneous Memory Management: the CPU's MMU and the GPU's IOMMU share the same address space.[17][18]2014
PlayStation 4,
Kaveri APUs		CPU and GPU now access the memory with the same address space. Pointers can now be freely passed between CPU and GPU, hence enabling zero-copy.
Fully coherent memory between CPU and GPUGPU can now access and cache data from coherent memory regions in the system memory, and also reference the data from CPU's cache. Cache coherency is maintained.
GPU uses pageable system memory via CPU pointersGPU can take advantage of the shared virtual memory between CPU and GPU, and pageable system memory can now be referenced directly by the GPU, instead of being copied or pinned before accessing.
System IntegrationGPU compute context switch2015
Carrizo APU		Compute tasks on GPU can be context switched, allowing a multi-tasking environment and also faster interpretation between applications, compute and graphics.
GPU graphics pre-emptionLong-running graphics tasks can be pre-empted so processes have low latency access to the GPU.
Quality of service[17]In addition to context switch and pre-emption, hardware resources can be either equalized or prioritized among multiple users and applications.

Feature overview

The following table shows features of AMD's processors with 3D graphics, including APUs (see also: List of AMD processors with 3D graphics).

Platform High, standard and low power Low and ultra-low power
CodenameServer Basic Toronto
Micro Kyoto
Desktop Performance Raphael
Mainstream Llano Trinity Richland Kaveri Kaveri Refresh (Godavari) Carrizo Bristol Ridge Raven Ridge Picasso Renoir Cezanne
Entry
Basic Kabini Dalí
MobilePerformance Renoir Cezanne Rembrandt Dragon Range
Mainstream Llano Trinity Richland Kaveri Carrizo Bristol Ridge Raven Ridge Picasso Renoir
Lucienne		 Cezanne
Barceló		 Phoenix
Entry Dalí Mendocino
Basic Desna, Ontario, Zacate Kabini, Temash Beema, Mullins Carrizo-L Stoney Ridge Pollock
Embedded Trinity Bald Eagle Merlin Falcon,
Brown Falcon		 Great Horned Owl Grey Hawk Ontario, Zacate Kabini Steppe Eagle, Crowned Eagle,
LX-Family		 Prairie Falcon Banded Kestrel River Hawk
ReleasedAug 2011Oct 2012Jun 2013Jan 2014 2015Jun 2015Jun 2016Oct 2017Jan 2019Mar 2020 Jan 2021Jan 2022Sep 2022Jan 2023Jan 2011May 2013Apr 2014May 2015Feb 2016Apr 2019Jul 2020Jun 2022Nov 2022
CPU microarchitecture K10 Piledriver Steamroller Excavator "Excavator+"[19] Zen Zen+ Zen 2 Zen 3 Zen 3+ Zen 4 Bobcat Jaguar Puma Puma+[20] "Excavator+" Zen Zen+ "Zen 2+"
ISAx86-64 v1x86-64 v2x86-64 v3x86-64 v4x86-64 v1x86-64 v2x86-64 v3
Socket Desktop Performance — AM5 — —
Mainstream — AM4 — —
Entry FM1 FM2 FM2+ FM2+[lower-alpha 1], AM4 AM4 —
Basic — — AM1 — FP5 —
Other FS1 FS1+, FP2 FP3 FP4 FP5 FP6 FP7 FL1 FP7
FP7r2
FP8		 ? FT1 FT3 FT3b FP4 FP5 FT5 FP5 FT6
PCI Express version 2.0 3.0 4.0 5.0 4.0 2.0 3.0
CXL— —
Fab. (nm) GF 32SHP
(HKMG SOI)		 GF 28SHP
(HKMG bulk)		 GF 14LPP
(FinFET bulk)		 GF 12LP
(FinFET bulk)		 TSMC N7
(FinFET bulk)		 TSMC N6
(FinFET bulk)		 CCD: TSMC N5
(FinFET bulk)
cIOD: TSMC N6
(FinFET bulk)		 TSMC 4nm
(FinFET bulk)		 TSMC N40
(bulk)		 TSMC N28
(HKMG bulk)		 GF 28SHP
(HKMG bulk)		 GF 14LPP
(FinFET bulk)		 GF 12LP
(FinFET bulk)		 TSMC N6
(FinFET bulk)
Die area (mm2)228246245245250210[21]156 180210CCD: (2x) 70
cIOD: 122		 17875 (+ 28 FCH)107?125149~100
Min TDP (W)3517121015105354.543.95106128
Max APU TDP (W)10095654517054182565415
Max stock APU base clock (GHz)33.84.14.13.73.83.63.73.84.03.34.74.31.752.222.23.22.61.23.352.8
Max APUs per node[lower-alpha 2]11
Max core dies per CPU1211
Max CCX per core die1211
Max cores per CCX482424
Max CPU[lower-alpha 3] cores per APU481682424
Max threads per CPU core1212
Integer pipeline structure3+32+24+24+2+11+3+3+1+21+1+1+12+24+24+2+1
i386, i486, i586, CMOV, NOPL, i686, PAE, NX bit, CMPXCHG16B, AMD-V, RVI, ABM, and 64-bit LAHF/SAHFYes Yes
IOMMU[lower-alpha 4]—v2v1v2
BMI1, AES-NI, CLMUL, and F16C Yes—Yes
MOVBE—Yes
AVIC, BMI2, RDRAND, and MWAITX/MONITORX —Yes
SME[lower-alpha 5], TSME[lower-alpha 5], ADX, SHA, RDSEED, SMAP, SMEP, XSAVEC, XSAVES, XRSTORS, CLFLUSHOPT, CLZERO, and PTE Coalescing—Yes —Yes
GMET, WBNOINVD, CLWB, QOS, PQE-BW, RDPID, RDPRU, and MCOMMIT—Yes —Yes
MPK, VAES—Yes —
SGX——
FPUs per core10.5110.51
Pipes per FPU22
FPU pipe width128-bit256-bit80-bit128-bit256-bit
CPU instruction set SIMD levelSSE4a[lower-alpha 6]AVX AVX2AVX-512SSSE3AVXAVX2
3DNow!3DNow!+— —
PREFETCH/PREFETCHWYes Yes
GFNI—Yes —
AMX—
FMA4, LWP, TBM, and XOP—Yes— —Yes—
FMA3Yes Yes
AMD XDNA—Yes —
L1 data cache per core (KiB)64163232
L1 data cache associativity (ways)2488
L1 instruction caches per core10.51 10.51
Max APU total L1 instruction cache (KiB)256128192256512256 64128 96 128
L1 instruction cache associativity (ways)2348 2 3 4 8
L2 caches per core10.5110.51
Max APU total L2 cache (MiB)424161212
L2 cache associativity (ways)168168
Max on--die L3 cache per CCX (MiB)—41632—4
Max 3D V-Cache per CCD (MiB)—64——
Max total in-CCD L3 cache per APU (MiB)4816644
Max. total 3D V-Cache per APU (MiB)—64——
Max. board L3 cache per APU (MiB)——
Max total L3 cache per APU (MiB)48161284
APU L3 cache associativity (ways)1616
L3 cache schemeVictimVictim
Max. L4 cache——
Max stock DRAM supportDDR3-1866DDR3-2133DDR3-2133, DDR4-2400DDR4-2400DDR4-2933DDR4-3200, LPDDR4-4266DDR5-4800, LPDDR5-6400DDR5-5200DDR5-5600, LPDDR5x-7500DDR3L-1333DDR3L-1600DDR3L-1866DDR3-1866, DDR4-2400DDR4-2400DDR4-1600DDR4-3200LPDDR5-5500
Max DRAM channels per APU21212
Max stock DRAM bandwidth (GB/s) per APU29.86634.13238.40046.93268.256102.40083.200120.000 10.66612.80014.93319.20038.40012.80051.20088.000
GPU microarchitectureTeraScale 2 (VLIW5)TeraScale 3 (VLIW4)GCN 2nd genGCN 3rd genGCN 5th gen[22]RDNA 2RDNA 3TeraScale 2 (VLIW5)GCN 2nd genGCN 3rd gen[22]GCN 5th genRDNA 2
GPU instruction setTeraScale instruction setGCN instruction setRDNA instruction setTeraScale instruction setGCN instruction setRDNA instruction set
Max stock GPU base clock (MHz)60080084486611081250140021002400400 538600?847900120060013001900
Max stock GPU base GFLOPS[lower-alpha 7]480614.4648.1886.71134.517601971.22150.43686.4102.4 86???345.6460.8230.41331.2486.4
3D engine[lower-alpha 8]Up to 400:20:8Up to 384:24:6Up to 512:32:8Up to 704:44:16[23]Up to 512:32:8768:48:8128:8:480:8:4128:8:4Up to 192:12:8Up to 192:12:4192:12:4Up to 512:?:?128:?:?
IOMMUv1IOMMUv2IOMMUv1?IOMMUv2
Video decoderUVD 3.0UVD 4.2UVD 6.0VCN 1.0[24]VCN 2.1[25] VCN 2.2[25]VCN 3.1?UVD 3.0UVD 4.0UVD 4.2UVD 6.0UVD 6.3VCN 1.0VCN 3.1
Video encoder—VCE 1.0VCE 2.0VCE 3.1—VCE 2.0VCE 3.1
AMD Fluid Motion No Yes No No Yes No
GPU power savingPowerPlayPowerTunePowerPlayPowerTune[26]
TrueAudio—Yes[27]? —Yes
FreeSync1
2		 1
2
HDCP[lower-alpha 9]?1.42.22.3?1.42.22.3
PlayReady[lower-alpha 9]—3.0 not yet—3.0 not yet
Supported displays[lower-alpha 10]2–32–433 (desktop)
4 (mobile, embedded)		42344
/drm/radeon[lower-alpha 11][29][30]Yes— Yes—
/drm/amdgpu[lower-alpha 11][31]—Yes[32] —Yes[32]
  1. For FM2+ Excavator models: A8-7680, A6-7480 & Athlon X4 845.
  2. A PC would be one node.
  3. An APU combines a CPU and a GPU. Both have cores.
  4. Requires firmware support.
  5. Requires firmware support.
  6. No SSE4. No SSSE3.
  7. Single-precision performance is calculated from the base (or boost) core clock speed based on a FMA operation.
  8. Unified shaders : texture mapping units : render output units
  9. To play protected video content, it also requires card, operating system, driver, and application support. A compatible HDCP display is also needed for this. HDCP is mandatory for the output of certain audio formats, placing additional constraints on the multimedia setup.
  10. To feed more than two displays, the additional panels must have native DisplayPort support.[28] Alternatively active DisplayPort-to-DVI/HDMI/VGA adapters can be employed.
  11. DRM (Direct Rendering Manager) is a component of the Linux kernel. Support in this table refers to the most current version.

APU or Radeon Graphics branded platforms
For a more comprehensive list, see List of AMD processors with 3D graphics.

AMD APUs have CPU modules, cache, and a discrete-class graphics processor, all on the same die using the same bus. This architecture allows for the use of graphics accelerators, such as OpenCL, with the integrated graphics processor.[33] The goal is to create a "fully integrated" APU, which, according to AMD, will eventually feature 'heterogeneous cores' capable of processing both CPU and GPU work automatically, depending on the workload requirement.[34]

K10 architecture (2011): Llano
AMD A6-3650 (Llano)
Main article: AMD 10h

The first generation APU, released in June 2011, was used in both desktops and laptops. It was based on the K10 architecture and built on a 32 nm process featuring two to four CPU cores on a thermal design power (TDP) of 65-100 W, and integrated graphics based on the Radeon HD6000 Series with support for DirectX 11, OpenGL 4.2 and OpenCL 1.2. In performance comparisons against the similarly priced Intel Core i3-2105, the Llano APU was criticised for its poor CPU performance[37] and praised for its better GPU performance.[38][39] AMD was later criticised for abandoning Socket FM1 after one generation.[40]

Bobcat architecture (2011): Ontario, Zacate, Desna, Hondo
Main article: Bobcat (microarchitecture)

The AMD Brazos platform was introduced on 4 January 2011, targeting the subnotebook, netbook and low power small form factor markets.[3] It features the 9-watt AMD C-Series APU (codename: Ontario) for netbooks and low power devices as well as the 18-watt AMD E-Series APU (codename: Zacate) for mainstream and value notebooks, all-in-ones and small form factor desktops. Both APUs feature one or two Bobcat x86 cores and a Radeon Evergreen Series GPU with full DirectX11, DirectCompute and OpenCL support including UVD3 video acceleration for HD video including 1080p.[3]

AMD expanded the Brazos platform on 5 June 2011 with the announcement of the 5.9-watt AMD Z-Series APU (codename: Desna) designed for the Tablet market.[41] The Desna APU is based on the 9-watt Ontario APU. Energy savings were achieved by lowering the CPU, GPU and northbridge voltages, reducing the idle clocks of the CPU and GPU as well as introducing a hardware thermal control mode.[41] A bidirectional turbo core mode was also introduced.

AMD announced the Brazos-T platform on 9 October 2012. It comprised the 4.5-watt AMD Z-Series APU (codenamed Hondo) and the A55T Fusion Controller Hub (FCH), designed for the tablet computer market.[42][43] The Hondo APU is a redesign of the Desna APU. AMD lowered energy use by optimizing the APU and FCH for tablet computers.[44][45]

The Deccan platform including Krishna and Wichita APUs were cancelled in 2011. AMD had originally planned to release them in the second half 2012.[46]

Piledriver architecture (2012): Trinity and Richland
Piledriver-based AMD APUs
An AMD A4-5300 for desktop systems
An AMD A10-4600M for mobile systems
Main article: Piledriver (microarchitecture)
Trinity

The first iteration of the second generation platform, released in October 2012, brought improvements to CPU and GPU performance to both desktops and laptops. The platform features 2 to 4 Piledriver CPU cores built on a 32 nm process with a TDP between 65 W and 100 W, and a GPU based on the Radeon HD7000 Series with support for DirectX 11, OpenGL 4.2, and OpenCL 1.2. The Trinity APU was praised for the improvements to CPU performance compared to the Llano APU.[49]

Richland
  • "Enhanced Piledriver" CPU cores[50]
  • Temperature Smart Turbo Core technology. An advancement of the existing Turbo Core technology, which allows internal software to adjust the CPU and GPU clock speed to maximise performance within the constraints of the Thermal design power of the APU.[51]
  • New low-power consumption CPUs with only 45 W TDP[52]

The release of this second iteration of this generation was 12 March 2013 for mobile parts and 5 June 2013 for desktop parts.

Jaguar architecture (2013): Kabini and Temash
Main article: Jaguar (microarchitecture)

In January 2013 the Jaguar-based Kabini and Temash APUs were unveiled as the successors of the Bobcat-based Ontario, Zacate and Hondo APUs.[53][54][55] The Kabini APU is aimed at the low-power, subnotebook, netbook, ultra-thin and small form factor markets, while the Temash APU is aimed at the tablet, ultra-low power and small form factor markets.[55] The two to four Jaguar cores of the Kabini and Temash APUs feature numerous architectural improvements regarding power requirement and performance, such as support for newer x86-instructions, a higher IPC count, a CC6 power state mode and clock gating.[56][57][58] Kabini and Temash are AMD's first, and also the first ever quad-core x86 based SoCs.[59] The integrated Fusion Controller Hubs (FCH) for Kabini and Temash are codenamed "Yangtze" and "Salton", respectively.[60] The Yangtze FCH features support for two USB 3.0 ports, two SATA 6 Gbit/s ports, as well as the xHCI 1.0 and SD/SDIO 3.0 protocols for SD-card support.[60] Both chips feature DirectX 11.1-compliant GCN-based graphics as well as numerous HSA improvements.[53][54] They were fabricated at a 28 nm process in an FT3 ball grid array package by Taiwan Semiconductor Manufacturing Company (TSMC), and were released on 23 May 2013.[56][61][62]

The PlayStation 4 and Xbox One were revealed to both be powered by 8-core semi-custom Jaguar-derived APUs.

Steamroller architecture (2014): Kaveri
AMD A8-7650K (Kaveri)
Main article: Steamroller (microarchitecture)

The third generation of the platform, codenamed Kaveri, was partly released on 14 January 2014.[65] Kaveri contains up to four Steamroller CPU cores clocked to 3.9 GHz with a turbo mode of 4.1 GHz, up to a 512-core Graphics Core Next GPU, two decode units per module instead of one (which allows each core to decode four instructions per cycle instead of two), AMD TrueAudio,[66] Mantle API,[67] an on-chip ARM Cortex-A5 MPCore,[68] and will release with a new socket, FM2+.[69] Ian Cutress and Rahul Garg of Anandtech asserted that Kaveri represented the unified system-on-a-chip realization of AMD's acquisition of ATI. The performance of the 45 W A8-7600 Kaveri APU was found to be similar to that of the 100 W Richland part, leading to the claim that AMD made significant improvements in on-die graphics performance per watt;[63] however, CPU performance was found to lag behind similarly specified Intel processors, a lag that was unlikely to be resolved in the Bulldozer family APUs.[63] The A8-7600 component was delayed from a Q1 launch to an H1 launch because the Steamroller architecture components allegedly did not scale well at higher clock speeds.[70]

AMD announced the release of the Kaveri APU for the mobile market on 4 June 2014 at Computex 2014,[64] shortly after the accidental announcement on the AMD website on 26 May 2014.[71] The announcement included components targeted at the standard voltage, low-voltage, and ultra-low voltage segments of the market. In early-access performance testing of a Kaveri prototype laptop, AnandTech found that the 35 W FX-7600P was competitive with the similarly priced 17 W Intel i7-4500U in synthetic CPU-focused benchmarks, and was significantly better than previous integrated GPU systems on GPU-focused benchmarks.[72] Tom's Hardware reported the performance of the Kaveri FX-7600P against the 35 W Intel i7-4702MQ, finding that the i7-4702MQ was significantly better than the FX-7600P in synthetic CPU-focused benchmarks, whereas the FX-7600P was significantly better than the i7-4702MQ's Intel HD 4600 iGPU in the four games that could be tested in the time available to the team.[64]

Puma architecture (2014): Beema and Mullins
Main article: Puma (microarchitecture)

Puma+ architecture (2015): Carrizo-L
Main article: Puma (microarchitecture) § Puma+

Excavator architecture (2015): Carrizo
Main article: Excavator (microarchitecture)

Steamroller architecture (Q2–Q3 2015): Godavari
Main article: Steamroller (microarchitecture)
  • Update of the desktop Kaveri series with higher clock frequencies or smaller power envelope
  • Steamroller-based CPU with 4 cores[76]
  • Graphics Core Next 2nd Gen-based GPU
  • Memory controller supports DDR3 SDRAM at 2133 MHz
  • 65/95 W TDP with support for configurable TDP
  • Socket FM2+
  • Target segment desktop
  • Listed since Q2 2015

Excavator architecture (2016): Bristol Ridge and Stoney Ridge
AMD A12-9800 (Bristol Ridge)
Main article: Excavator (microarchitecture)
  • Excavator-based CPU with 2–4 cores
  • 1 MB L2 cache per module
  • Graphics Core Next 3rd Gen-based GPU[77][78][79][80]
  • Memory controller supports DDR4 SDRAM
  • 15/35/45/65 W TDP with support for configurable TDP
  • 28 nm
  • Socket AM4 for desktop
  • Target segment desktop, mobile and ultra-mobile

Zen architecture (2017): Raven Ridge
Main articles: Zen (microarchitecture) and Ryzen § APUs: Raven Ridge

Zen+ architecture (2019): Picasso
Main articles: Zen+ and Ryzen § APUs: Picasso
  • Zen+-based CPU microarchitecture[85]
  • Refresh of Raven Ridge on 12 nm with improved latency and efficiency/clock frequency. Features similar to Raven Ridge
  • Launched January 2019

Zen 2 architecture (2020): Renoir
Main articles: Zen 2 and Renoir APUs

Zen 3 architecture (2021): Cezanne
Main articles: Zen 3 and Cezanne APUs

Zen 3+ architecture (2022): Rembrandt
  • Zen 3+ based CPU microarchitecture[91]
  • RDNA 2-based GPU[91]
  • Memory controller supports DDR5-4800 and LPDDR5-6400[91]
  • Up to 45 W TDP for mobile
  • Node: TSMC N6[91]
  • Socket FP7 for mobile
  • Released for mobiles early 2022[91]

See also

References
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