ARM Cortex-M

ARM Limited neither manufactures nor sells CPU devices based on its own designs, but rather licenses the processor architecture to interested parties. Arm offers a variety of licensing terms, varying in cost and deliverables. To all licensees, Arm provides an integratable hardware description of the ARM core, as well as complete software development toolset and the right to sell manufactured silicon containing the ARM CPU.

Integrated Device Manufacturers (IDM) receive the ARM Processor IP as synthesizable RTL (written in Verilog). In this form, they have the ability to perform architectural level optimizations and extensions. This allows the manufacturer to achieve custom design goals, such as higher clock speed, very low power consumption, instruction set extensions (including floating point), optimizations for size, debug support, etc. To determine which components have been included in a particular ARM CPU chip, consult the manufacturer datasheet and related documentation.

Some of the silicon options for the Cortex-M cores are:

• SysTick timer: A 24-bit system timer that extends the functionality of both the processor and the Nested Vectored Interrupt Controller (NVIC). When present, it also provides an additional configurable priority SysTick interrupt.[13][14][15] Though the SysTick timer is optional for the M0/M0+/M1/M23, it is extremely rare to find a Cortex-M microcontroller without it. If a Cortex-M33/M35P/M55/M85 microcontroller has the Security Extension option, then it optionally can have two SysTicks (one Secure, one Non-secure).
• Bit-Band: Maps a complete word of memory onto a single bit in the bit-band region. For example, writing to an alias word will set or clear the corresponding bit in the bit-band region. This allows every individual bit in the bit-band region to be directly accessible from a word-aligned address. In particular, individual bits can be set, cleared, or toggled from C/C++ without performing a read-modify-write sequence of instructions.[13][14][15] Though the bit-band is optional, it is less common to find a Cortex-M3 and Cortex-M4 microcontroller without it. Some Cortex-M0 and Cortex-M0+ microcontrollers have bit-band.
• Memory Protection Unit (MPU): Provides support for protecting regions of memory through enforcing privilege and access rules. It supports up to sixteen different regions, each of which can be split further into equal-size sub-regions.[13][14][15]
• Tightly-Coupled Memory (TCM): Low-latency (zero wait state) SRAM that can be used to hold the call stack, RTOS control structures, interrupt data structures, interrupt handler code, and speed critical code. Other than CPU cache, TCM is the fastest memory in an ARM Cortex-M microcontroller. Since TCM isn't cached and accessible at the same speed as the processor and cache, it could be conceptually described as "addressable cache". There is an ITCM (Instruction TCM) and a DTCM (Data TCM) to allow a Harvard architecture processor to read from both simultaneously. The DTCM can't contain any instructions, but the ITCM can contain data. Since TCM is tightly connected to the processor core, DMA engines might not be able to access TCM on some implementations.

• Note: Most Cortex-M3 and M4 chips have bit-band and MPU. The bit-band option can be added to the M0/M0+ using the Cortex-M System Design Kit.[26]
• Note: Software should validate the existence of each feature before attempting to use it.[15]
• Note: Limited public information is available for the Cortex-M35P until its Technical Reference Manual is released.

Additional silicon options:[13][14]

• Data endianness: Little-endian or big-endian. Unlike legacy ARM cores, the Cortex-M is permanently fixed in silicon as one of these choices.
• Interrupts: 1 to 32 (M0/M0+/M1), 1 to 240 (M3/M4/M7/M23), 1 to 480 (M33/M35P/M55/M85).
• Wake-up interrupt controller: Optional.
• Vector Table Offset Register: Optional. (not available for M0).
• Instruction fetch width: 16-bit only, or mostly 32-bit.
• User/privilege support: Optional.
• Reset all registers: Optional.
• Single-cycle I/O port: Optional. (M0+/M23).
• Debug Access Port (DAP): None, SWD, JTAG and SWD. (optional for all Cortex-M cores)
• Halting debug support: Optional.
• Number of watchpoint comparators: 0 to 2 (M0/M0+/M1), 0 to 4 (M3/M4/M7/M23/M33/M35P/M55/M85).
• Number of breakpoint comparators: 0 to 4 (M0/M0+/M1/M23), 0 to 8 (M3/M4/M7/M33/M35P/M55/M85).

The Cortex-M0 / M0+ / M1 implement the ARMv6-M architecture,[13] the Cortex-M3 implements the ARMv7-M architecture,[14] the Cortex-M4 / Cortex-M7 implements the ARMv7E-M architecture,[14] the Cortex-M23 / M33 / M35P implement the ARMv8-M architecture,[28] and the Cortex-M55 / M85 implements the ARMv8.1-M architecture.[28] The architectures are binary instruction upward compatible from ARMv6-M to ARMv7-M to ARMv7E-M. Binary instructions available for the Cortex-M0 / Cortex-M0+ / Cortex-M1 can execute without modification on the Cortex-M3 / Cortex-M4 / Cortex-M7. Binary instructions available for the Cortex-M3 can execute without modification on the Cortex-M4 / Cortex-M7 / Cortex-M33 / Cortex-M35P.[13][14] Only Thumb-1 and Thumb-2 instruction sets are supported in Cortex-M architectures; the legacy 32-bit ARM instruction set isn't supported.

All Cortex-M cores implement a common subset of instructions that consists of most Thumb-1, some Thumb-2, including a 32-bit result multiply. The Cortex-M0 / Cortex-M0+ / Cortex-M1 / Cortex-M23 were designed to create the smallest silicon die, thus having the fewest instructions of the Cortex-M family.

The Cortex-M0 / M0+ / M1 include Thumb-1 instructions, except new instructions (CBZ, CBNZ, IT) which were added in ARMv7-M architecture. The Cortex-M0 / M0+ / M1 include a minor subset of Thumb-2 instructions (BL, DMB, DSB, ISB, MRS, MSR).[13] The Cortex-M3 / M4 / M7 / M33 / M35P have all base Thumb-1 and Thumb-2 instructions. The Cortex-M3 adds three Thumb-1 instructions, all Thumb-2 instructions, hardware integer divide, and saturation arithmetic instructions. The Cortex-M4 adds DSP instructions and an optional single-precision floating-point unit (VFPv4-SP). The Cortex-M7 adds an optional double-precision FPU (VFPv5).[21][14] The Cortex-M23 / M33 / M35P / M55 / M85 add TrustZone instructions.

• Note: Interrupt latency cycle count assumes: 1) stack located in zero-wait state RAM, 2) another interrupt function not currently executing, 3) Security Extension option doesn't exist, because it adds additional cycles. The Cortex-M cores with a Harvard computer architecture have a shorter interrupt latency than Cortex-M cores with a Von Neumann computer architecture.
• Note: The Cortex-M series includes three new 16-bit Thumb-1 instructions for sleep mode: SEV, WFE, WFI.
• Note: The Cortex-M0 / M0+ / M1 doesn't include these 16-bit Thumb-1 instructions: CBZ, CBNZ, IT.[13][14]
• Note: The Cortex-M0 / M0+ / M1 only include these 32-bit Thumb-2 instructions: BL, DMB, DSB, ISB, MRS, MSR.[13][14]
• Note: The Cortex-M0 / M0+ / M1 / M23 only has 32-bit multiply instructions with a lower-32-bit result (32 bit × 32 bit = lower 32 bit), where as the Cortex-M3 / M4 / M7 / M33 / M35P includes additional 32-bit multiply instructions with 64-bit results (32 bit × 32 bit = 64 bit). The Cortex-M4 / M7 (optionally M33 / M35P) include DSP instructions for (16 bit × 16 bit = 32 bit), (32 bit × 16 bit = upper 32 bit), (32 bit × 32 bit = upper 32 bit) multiplications.[13][14]
• Note: The number of cycles to complete multiply and divide instructions vary across ARM Cortex-M core designs. Some cores have a silicon option for the choice of fast speed or small size (slow speed), so cores have the option of using less silicon with the downside of higher cycle count. An interrupt occurring during the execution of a divide instruction or slow-iterative multiply instruction will cause the processor to abandon the instruction, then restart it after the interrupt returns.
  • Multiply instructions "32-bit result" – Cortex-M0/M0+/M23 is 1 or 32 cycle silicon option, Cortex-M1 is 3 or 33 cycle silicon option, Cortex-M3/M4/M7/M33/M35P is 1 cycle.
  • Multiply instructions "64-bit result" – Cortex-M3 is 3–5 cycles (depending on values), Cortex-M4/M7/M33/M35P is 1 cycle.
  • Divide instructions – Cortex-M3/M4 is 2–12 cycles (depending on values), Cortex-M7 is 3–20 cycles (depending on values), Cortex-M23 is 17 or 34 cycle option, Cortex-M33 is 2–11 cycles (depending on values), Cortex-M35P is TBD.
• Note: Some Cortex-M cores have silicon options for various types of floating point units (FPU). The Cortex-M55 / M85 has an option for half-precision (HP), the Cortex-M4 / M7 / M33 / M35P / M55 / M85 has an option for single-precision (SP), the Cortex-M7 / M55 / M85 has an option for double-precision (DP). When an FPU is included, the core is sometimes referred as "Cortex-MxF", where 'x' is the core variant, such as Cortex-M4F.[13][14]

• Note: MOVW is an alias that means 32-bit "wide" MOV instruction.
• Note: For Cortex-M1, WFE / WFI / SEV instructions exist, but execute as a NOP instruction.
• Note: The half-precision (HP) FPU instructions are valid in the Cortex-M55 / M85 only when the HP FPU option exists in the silicon.
• Note: The single-precision (SP) FPU instructions are valid in the Cortex-M4 / M7 / M33 / M35P / M55 / M85 only when the SP FPU option exists in the silicon.
• Note: The double-precision (DP) FPU instructions are valid in the Cortex-M7 / M55 / M85 only when the DP FPU option exists in the silicon.

The ARM architecture for ARM Cortex-M series removed some features from older legacy cores:[13][14]

• The 32-bit ARM instruction set is not included in Cortex-M cores.
• Endianness is chosen at silicon implementation in Cortex-M cores. Legacy cores allowed "on-the-fly" changing of the data endian mode.
• Co-processors were not supported on Cortex-M cores, until the silicon option was reintroduced in "ARMv8-M Mainline" for ARM Cortex-M33/M35P cores.

The capabilities of the 32-bit ARM instruction set is duplicated in many ways by the Thumb-1 and Thumb-2 instruction sets, but some ARM features don't have a similar feature:

• The SWP and SWPB (swap) ARM instructions don't have a similar feature in Cortex-M.

The 16-bit Thumb-1 instruction set has evolved over time since it was first released in the legacy ARM7T cores with the ARMv4T architecture. New Thumb-1 instructions were added as each legacy ARMv5 / ARMv6 / ARMv6T2 architectures were released. Some 16-bit Thumb-1 instructions were removed from the Cortex-M cores:

• The "BLX <immediate>" instruction doesn't exist because it was used to switch from Thumb-1 to ARM instruction set. The "BLX <register>" instruction is still available in the Cortex-M.
• SETEND doesn't exist because on-the-fly switching of data endian mode is no longer supported.
• Co-processor instructions were not supported on Cortex-M cores, until the silicon option was reintroduced in "ARMv8-M Mainline" for ARM Cortex-M33/M35P cores.
• The SWI instruction was renamed to SVC, though the instruction binary coding is the same. However, the SVC handler code is different from the SWI handler code, because of changes to the exception models.

nRF51822

The following microcontrollers are based on the Cortex-M0 core:

• ABOV AC30M1x64
• Cypress PSoC 4000, 4100, 4100M, 4200, 4200DS, 4200L, 4200M
• Infineon XMC1100, XMC1200, XMC1300, XMC1400, TLE984x
• Dialog DA1458x, DA1468x
• Nordic nRF51
• NXP LPC1100, LPC1200
• Nuvoton NuMicro
• Sonix SN32F700
• ST STM32 F0
• Toshiba TX00
• Vorago VA10800 (extreme temperature), VA10820 (radiation hardened)

The following chips have a Cortex-M0 as a secondary core:

• NXP LPC4300 (one Cortex-M4F + one Cortex-M0)
• Texas Instruments SimpleLink Wireless MCUs CC1310 and CC2650 (one programmable Cortex-M3 + one Cortex-M0 network processor + one proprietary Sensor Controller Engine)

The following microcontrollers are based on the Cortex-M0+ core:

• ABOV Semiconductor A31G11x, A31G12x, A31G314
• Cypress PSoC 4000S, 4100S, 4100S+, 4100PS, 4700S, FM0+
• Epson S1C31W74, S1C31D01, S1C31D50
• Holtek HT32F52000
• Microchip SAM C2, D0, D1, D2, DA, L2, R2, R3 and PIC 32CMJH
• NXP LPC800, LPC11E60, LPC11U60
• NXP (Freescale) Kinetis E, EA, L, M, V1, W0, S32K11x
• Raspberry Pi RP2040 (two M0+ cores)
• Renesas S124, S128, RE, RE01
• Silicon Labs (Energy Micro) EFM32 Zero, Happy
• ST STM32 L0, G0, C0, WL (one Cortex-M4 + one Cortex-M0+)

The following chips have a Cortex-M0+ as a secondary core:

• Cypress PSoC 6200 (one Cortex-M4F + one Cortex-M0+)
• ST WB (one Cortex-M4F + one Cortex-M0+)

The smallest ARM microcontrollers are of the Cortex-M0+ type (as of 2014, smallest at 1.6 mm by 2 mm in a chip-scale package is Kinetis KL03).[29]

On 21 June 2018, the "world's smallest computer'", or computer device was announced – based on the ARM Cortex-M0+ (and including RAM and wireless transmitters and receivers based on photovoltaics) – by University of Michigan researchers at the 2018 Symposia on VLSI Technology and Circuits with the paper "A 0.04mm³ 16nW Wireless and Batteryless Sensor System with Integrated Cortex-M0+ Processor and Optical Communication for Cellular Temperature Measurement." The device is one-tenth the size of IBM's previously claimed world-record-sized computer from months back in March 2018, which is smaller than a grain of salt.

The following vendors support the Cortex-M1 as soft-cores on their FPGA chips:

• Altera Cyclone-II, Cyclone-III, Stratix-II, Stratix-III
• GOWIN M1 [30]
• Actel/Microsemi/Microchip Fusion, IGLOO/e, ProASIC3L, ProASIC3/E
• Xilinx Spartan-3, Virtex-2, Virtex-3, Virtex-4, Artix-7[31]

The following microcontrollers are based on the Cortex-M3 core:

• ABOV AC33Mx128, AC33Mx064
• Actel/Microsemi/Microchip SmartFusion, SmartFusion 2 (FPGA)
• Analog Devices ADUCM360, ADUCM361, ADUCM3029
• Broadcom Wi-Fi Chip BCM4319XKUBG
• Cypress PSoC 5000, 5000LP, FM3
• Holtek HT32F
• Infineon TLE9860, TLE987x
• Microchip (Atmel) SAM 3A, 3N, 3S, 3U, 3X
• NXP LPC1300, LPC1700, LPC1800
• ON Q32M210
• Realtek RTL8710
• Silicon Labs Precision32
• Silicon Labs (Energy Micro) EFM32 Tiny, Gecko, Leopard, Giant
• ST STM32 F1, F2, L1, W
• TDK-Micronas HVC4223F
• Texas Instruments F28, LM3, TMS470, OMAP 4, SimpleLink Wireless MCUs (CC1310 Sub-GHz and CC2650 BLE+Zigbee+6LoWPAN)
• Toshiba TX03

The following chips have a Cortex-M3 as a secondary core:

• Apple A9 (Cortex-M3 as integrated M9 motion co-processor)
• CSR Quatro 5300 (Cortex-M3 as co-processor)
• Samsung Exynos 7420 (Cortex-M3 as a DVS microcontroller)[33]
• Texas Instruments F28, LM3, TMS470, OMAP 4470 (one Cortex-A9 + two Cortex-M3)
• XMOS XS1-XA (seven xCORE + one Cortex-M3)

The following FPGAs include a Cortex-M3 core:

• Microsemi SmartFusion2 SoC

The following vendors support the Cortex-M3 as soft-cores on their FPGA chips:

• Altera Cyclone-II, Cyclone-III, Stratix-II, Stratix-III
• Xilinx Spartan-3, Virtex-2, Virtex-3, Virtex-4, Artix-7[34]

nRF52833 on a micro bit v2

STM32F407IGH6

The following microcontrollers are based on the Cortex-M4 core:

• Analog Devices ADSP-CM40x
• Microchip (Atmel) SAM 4L, 4N, 4S
• NXP (Freescale) Kinetis K, W2
• ST (STM32) WL (one Cortex-M4 + one Cortex-M0+)
• Texas Instruments SimpleLink Wi-Fi CC32xx, CC32xxMOD

The following microcontrollers are based on the Cortex-M4F (M4 + FPU) core:

• Analog Devices ADUCM4050
• Cypress 6200 (one Cortex-M4F + one Cortex-M0+), FM4
• Infineon XMC4000
• Maxim Darwin
• Microchip (Atmel) SAM4C (Dual core: one Cortex-M4F + one Cortex-M4), SAM4E, SAM4L, SAM4N, SAM4S, SAMG5, SAMD5/E5x
• Nordic nRF52
• Nuvoton NuMicro M480
• NXP LPC4000, LPC4300 (one Cortex-M4F + one Cortex-M0), LPC54000
• NXP (Freescale) Kinetis K, V3, V4, S32K14x
• Renesas S3, S5, S7, RA4, RA6
• Silicon Labs (Energy Micro) EFM32 Wonder
• ST STM32 F3, F4, L4, L4+, G4, WB (one Cortex-M4F + one Cortex-M0+)
• Texas Instruments LM4F, TM4C, MSP432, CC13x2R, CC1352P, CC26x2R
• Toshiba TX04

The following chips have either a Cortex-M4 or M4F as a secondary core:

• NXP (Freescale) Vybrid VF6 (one Cortex-A5 + one Cortex-M4F)
• NXP (Freescale) i.MX 6 SoloX (one Cortex-A9 + one Cortex-M4F)
• NXP (Freescale) i.MX 7 Solo/Dual (one or two Cortex-A7 + one Cortex-M4F)
• NXP (Freescale) i.MX 8 (two Cortex-A72 + four Cortex-A53 + two Cortex-M4F)
• NXP (Freescale) i.MX 8M and 8M Mini (four Cortex-A53 + one Cortex-M4F)
• NXP (Freescale) i.MX 8X (four Cortex-A35 + one Cortex-M4F)
• ST STM32MP1 (one or two Cortex-A7 + one Cortex-M4)
• Texas Instruments OMAP 5 (two Cortex-A15s + two Cortex-M4)
• Texas Instruments Sitara AM5700 (one or two Cortex-A15s + two Cortex-M4s as image processing units + two Cortex-M4s as general purpose units)

The following microcontrollers are based on the Cortex-M7 core:

• Microchip (Atmel) SAM E7, S7, V7
• NXP (Freescale) Kinetis KV5x, i.MX RT, S32K3xx
• ST STM32 F7, H7

The following microcontrollers are based on the Cortex-M23 core:

• GigaDevice GD32E230
• Microchip SAM L10, L11 and PIC 32CM-LE 32CM-LS
• Nuvoton M2351
• Renesas S1JA, RA2A1, RA2L1, RA2E1, RA2E2

The following microcontrollers are based on the Cortex-M33 core:

• Analog Devices ADUCM410, ADUCM420
• Dialog DA1469x
• GigaDevice GD32E50x, GD32W515
• Nordic nRF91, nRF5340
• NXP LPC5500, i.MX RT600
• ON RSL15
• Renesas RA4, RA6
• ST STM32 H5, L5, U5, WBA
• Silicon Labs Wireless Gecko Series 2

The following microcontrollers are based on the Cortex-M35P core:

• STMicroelectronics ST33K1

• Alif Semiconductor Ensemble MCU families offer single or dual Cortex-M55 cores, each paired with Ethos-U55 NPUs

• Renesas RA8M1