VEGA Microprocessors

VEGA ET1031 is a compact and efficient 32-bit, 3-stage in-order processor based on RISC-V Instruction Set Architecture. This microprocessor can be used as an effective work horse in low power IoT applications. It is based on RISC-V (RV32IM) Instruction Set Architecture and contains a high-performance multiply/divide unit, configurable AXI4 or AHB external interface, optional MPU (Memory Protection Unit), Platform Level Interrupt Controller and advanced Integrated Debug Controller.

VEGA AS1061 is a 64-bit, 6 stage in-order pipelined processor based on RISC-V 64GC (RV64IMAFDC) Instruction Set Architecture. Its usage mainly aimed at low power embedded applications. The core has a highly optimized 6-stage in-order pipeline with supervisor support and has the capability to boot Linux or other Operating systems. The pipeline is highly configurable and can support the RISC-V RV64 IMAFDC extensions. The AXI or AHB standard interface provided enables ease of system integration and a JTAG interface is provided for debug support. It also supports a highly optimized branch predictor with BTB, BHT and RAS along with Optional Memory Management Unit (MMU), Configurable, L1 caches, Platform Level Interrupt Controller etc.

VEGA AS1161 features an out-of-order processing engine with a 16-stage pipeline enabling it to meet next gen computational requirements. The design supports RISC-V 64G (RV64IMAFD) Instruction Set Architecture in a 13-16 stage out-of-order pipeline implementation. The processor supports single and double precision floating point instructions, and a fully featured memory with Memory Management Unit and Page-based virtual memory for Linux-based applications. AS1161 is optimized for high performance, integrating an Advanced branch predictor for efficient branch execution, Instruction and Data caches. Features also include PLIC and vectored interrupts for serving various types of system events. An AXI4- / ACE, AHB- compliant external interface facilitates ease of system integration. There is also a WFI mode for power management, and JTAG debug interface for development support.

VEGA AS2161 features a dual core out-of-order processing engine with a 16-stage pipeline for high performance compute requirements. The design supports RISC-V 64G (RV64IMAFD) Instruction Set Architecture in a 13-16 stage out-of-order pipeline implementation. The processor also supports single and double precision floating point instructions, and MMU for Linux-based applications. This high-performance application core comes with advanced branch prediction for efficient branch execution, Instruction and Data caches. This is ideal for applications requiring high-throughput performance e.g., Media server, Single Board Computer, Storage, Networking etc. A Cache coherent interconnect along with a highly optimized L2 cache is also part of the design.

VEGA AS4161 features a quad core out-of-order processing engine with a 16-stage pipeline for high performance compute requirements. The design supports RISC-V 64G (RV64IMAFD) Instruction Set Architecture in a 13-16 stage out-of-order pipeline implementation along with advanced branch prediction unit, L1 Caches, MMU, TLB etc. This is ideal for applications requiring high-throughput performance e.g., Storage, Networking, etc. An AXI4- / ACE, AHB- compliant external interface is used to connect multiple cores to the interconnect and memory subsystem. A Cache coherent interconnect along with a highly optimized L2 cache is a part of the design.

THEJAS32 SoC [13] is built around VEGA ET1031, a 32-bit high performance microcontroller class processor consisting of a 3-stage in-order RISC-V based core. The peripherals available in THEJAS32 SoC are GPIO, Interrupt Controller, Timers, RAM, SPI, UART, I2C, PWM and ADC. This is targeted for applications like sensor fusion, smart meters, small IoT devices, wearable devices, electronic toys, etc. This SoC is ported on to Digilent Artix-7 35T FPGA Development Board, extensively used by the Swadeshi Microprocessor Challenge Participants. Also THEAJS32 SoC ASIC fabricated in SilTerra 130 nm technology.

THEJAS64 SoC [13] is built around VEGA AS1061, a 64-bit processor with a 6-stage in-order pipeline optimized for high performance. This processor consists of an efficient branch predictor and instruction and data caches and is targeted for applications like IoT devices, motor control, wearable devices, high-performance embedded, consumer electronics and industrial automation. The peripherals available in this SoC are GPIO, Interrupt Controller, Timers, DDR3 RAM, SPI, UART, I2C, PWM, ADC and 10/100 Ethernet. This SoC is ported on to Digilent Artix-7 100T, Nexys A7, Genesys2 FPGA Development Boards, extensively used by the Swadeshi Microprocessor Challenge Participants.

THEAJS32 ASIC fabricated in SilTerra 130 nm technology which operates at a frequency of 100 MHz. THEJAS32 SoC includes VEGA ET1031 Microprocessor, 256KB internal SRAM, Three UARTs, Four SPIs, Three TIMERs, Eight PWMs, Three I2C interface, 32 GPIOs etc.[18][17]

The ARIES MICRO v1.0 is a high-performance development board with loads of features in a small form factor. This breadboard friendly development platform based on THEAJS32 ASIC which operates at a frequency of 100 MHz.

Technical Specification

VEGA ARIES V2 Board

The ARIES v2.0 is a fully indigenous and a “Made in India” product to get started with basic microprocessor programming and embedded systems. This development board is built upon a RISC-V ISA compliant VEGA Processor with easy-to-use hardware and software.

Technical Specification

ARIES IoT v1.0 Board

ARIES IoT V1.0 is a feature-rich indigenous hardware platform based on THEAJS32 SoC which includes VEGA ET1031 Microprocessor. This board is targeted for learning and development of Internet of Things applications.