Futurebus

In the late 1970s, VMEbus was faster than the parts plugged into it. It was quite reasonable to connect a CPU and RAM to VME on separate cards to build a computer. However, as the speed of the CPUs and RAM rapidly increased, VME was quickly overwhelmed. Increasing the speed of VME was not easy, because all of the parts plugged into it would have to be able to support these faster speeds as well.

Futurebus looked to fix these problems and create a successor to systems like VMEbus with a system that could grow in speed without affecting existing devices. In order to do this the primary technology of Futurebus was built using asynchronous links, allowing the devices plugged into it to talk at whatever speed they wished. Another problem that needed to be addressed was the ability to have several cards in the system as "masters", allowing Futurebus to build multiprocessor machines. This required some form of "distributed arbitration" to allow the various cards to gain access to the bus at any point, as opposed to VME, which put a single master in slot 0 with overall control. In order to have a clear performance benefit, Futurebus was designed to have the performance needed ten years in the future.

Typical IEEE standards start with a company building a device, and then submitting it to the IEEE for the standardization effort. In the case of Futurebus this was reversed, the whole system was being designed during the standardization effort. This proved to be its downfall. As companies came to see Futurebus as the system, they all joined in. Soon the standards meetings had hundreds of people attending, all of them demanding that their particular needs and wants be included. As the complexity grew, the standards process slowed. In the end it took eight long years before the specification was finally agreed on in 1987. Tektronix did make a few workstations based on Futurebus.[1] American Logic Machines (ALM) continues to build end to end system Futurebus hybrid solutions, including VME-to-Futurebus+ and other Bus-to-Futurebus bridge technologies.

That was just in time for the US Navy who had been looking for a new high-speed system for the Next Generation Computer Resources (NGCR) project for passing sonar data around in their newly designed Seawolf-class submarines, and they said they would standardize on Futurebus if only a few more changes would be made. Seeing a potential massive government buy, the additions effort started immediately on Futurebus+. It took another four years for the Futurebus+ Standard to be released by this time custom variation of Futurebus took the lead in industry.

All of the Futurebus+ proponents had their idea of what Futurebus+ should be. This degenerated into "profiles", different versions of Futurebus+ targeted towards a particular market. Boards that were compliant with one Futurebus+ profile were not guaranteed to work with boards built to a different profile. The Futurebus+ standards development politics got so complicated that the IEEE 896 committee split from the IEEE Microcomputer Standards Committee and formed the IEEE Bus Architecture Standards Committee (BASC).

In the end very little use of Futurebus was attempted. The decade-long performance gap they gave the system had evaporated in the decade-long standards process, and conventional local bus systems like PCI were close in performance terms. Meanwhile, the VME ecosystem had evolved to such a degree that it continues to be used today, another decade on. Custom implementations of the Futurebus technology are currently used as backplane technologies for high-end network applications, enterprise class routers, high performance blade servers, and application with high demand-content such as video on demand.

Futurebus effort did act as a catalyst for simpler serial technologies. A group then organized to create a system aimed directly at this need, which eventually led to Scalable Coherent Interface (SCI). Meanwhile, another member decided to simple re-create the entire concept on a much simpler basis, which resulted in QuickRing. Due to the simplicity of these standards, both standards were completed before Futurebus+. Futurebus+ was ahead of its time in the 1980s. VME and other parallel bus standards are still trying to adapt concepts that are implemented in the Futurebus, specially in high performance applications.

Futurebus was the source of some of the original work on cache coherency, Live Insertion of boards, and Trapezoidal Transceivers. Trapezoidal Transceivers have a controlled risetime and make backplane and bus design much simpler. The original Trapezoidal Transceivers were made by National Semiconductor. Newer Futurebus+ transceivers that meet the IEEE Std 1194.1-1991 Backplane Transceiver Logic (BTL) standard are still made by Texas Instruments. Futurebus+ was used as the I/O bus in the DEC 4000 AXP and DEC 10000 AXP systems. Futurebus+ FDDI boards are still supported in the OpenVMS operating system. Futurebus+ custom chips support advanced Symmetric and Asymmetric versions of Unix-Like operating systems supported by companies such as American Logic Machines.

Many of the technical features (asynchronous data bus, distributed bus arbitration, large board size) are shared with IEEE standard FASTBUS. FASTBUS was used as a data acquisition system in many high-energy physics experiments in the 1980s and 1990s.

Futurebus is described in just a few IEEE standards:

• 896.1-1987 IEEE Standard Backplane Bus Specifications for Multiprocessor Architectures: Futurebus
• 1101-1987 IEEE Standard for Mechanical Core Specifications for Microcomputers Using IEC 603-2 Connectors

Futurebus systems were implemented with 9Ux280 Eurocard mechanics using 96-pin DIN connectors resulting in a backplane that supported both 16 and 32 bit bus widths.

To understand Futurebus+ you need to read many IEEE standards:

• 896.1-1991 IEEE Standard for Futurebus+ — Logical Protocol Specification
• 896.2-1991 IEEE Standard Backplane Bus Specification for Multiprocessor Architectures: Futurebus+
• 896.3-1993 IEEE recommended practice for Futurebus+
• 896.4-1993 IEEE Standard for Conformance Test Requirements for Futurebus+
• 896.5-1993 IEEE Standard for Futurebus+, Profile M (Military)
• 896.6 Futurebus+ telecommunications systems, profile T (telecommunications)
• 896.7 Interconnect between Futurebus+ systems
• 896.8 Small computer expandibility module for Futurebus+ systems, profile D (desktop)
• 896.9-1994 Fault tolerant extensions to the Futurebus+ architecture
• 896.10-1997 Standard for Futurebus+ Spaceborne Systems - Profile S
• 896.11 Standard for IEEE 1355 Links on Futurebus+ Backplane Connector
• 896.12 Standard for Fault Tolerance Classification of Computer-Based Systems
• 1194.1-1991 IEEE Standard for Electrical Characteristics of Backplane Transceiver Logic (BTL) Interface Circuits
• 1301 Standard for Metric Equipment Practice for Microcomputers - Coordination Document
• 1301.1-1991 IEEE Standard for a Metric Equipment Practice for Microcomputers—Convection-Cooled with 2 mm Connectors
• 1156.1 Standard Microprocessor Environmental Specifications for Computer Modules
• EIA IS-64 (1991) 2 mm Two-Part Connectors for Use with Printed Boards and Backplanes

896.2 contains three Profiles for target markets, A for general purpose systems, B for an I/O bus, and F for a Futurebus+ will all the options that will make it go fast. Profile A was sponsored by the VMEbus community. Profile B was sponsored by Digital Equipment Corporation and implemented in VAX and Alpha systems as an I/O bus. Profile F was sponsored by John Theus while he worked at Tektronix and was intended for high end workstations.

Futurebus+ supports bus widths from 32 to 256 bits. It is possible to build a board that supports all of these bus widths and will interoperate with boards that only support a subset. Split bus transactions are supported so that slow response to a read or write will not tie up the backplane bus. Cache Coherence, implemented using the MESI protocols, was very complicated but significantly improved performance. Futurebus+ was one of the first open standards to support Live Insertion which allowed boards to be replaced while the system was running.

Futurebus+ boards are 12SUx12SU Hard Metric size defined in the IEEE 1301 standards.

One of the most elegant features of the Futurebus design is its distributed bus arbitration mechanism. See US patent number 5060139 for more information. In the end this was replaced by a central arbiter.

• InfiniBand
• QuickRing
• Scalable Coherent Interconnect (SCI)
• Bus topology
• FASTBUS

• The Futurebus+ Handbook, John Theus, VITA
• Futurebus+ Handbook for Digital Systems, Digital Equipment Corporation

• Buses at the Wayback Machine (archived February 12, 2010)